Self-equalized and self-crosstalk-compensated 3D transmission line architecture with array of periodic bumps for high-speed single-ended signal transmission

Patent metadata

Field	Value
Publication number	US-11955436-B2
Application number	US-201916393304-A
Country	US
Kind code	B2
Filing date	Apr 24, 2019
Priority date	Apr 24, 2019
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.

First claim

What is claimed is:

1. A package substrate, comprising:
a dielectric over a conductive layer;
a conductive line on the dielectric;
a plurality of conductive bumps on a surface of the conductive line, wherein the plurality of conductive bumps are conductively coupled to the conductive line and are embedded in the dielectric;
a plurality of metal features on the plurality of conductive bumps, wherein individual ones of the plurality of metal features are on a corresponding individual one of the plurality of conductive bumps, and wherein the plurality of metal features has a metal conductivity different than that of the plurality of conductive bumps; and
a solder resist over the conductive line and the dielectric.

2. The package substrate of claim 1 , wherein the surface of the conductive line is a bottom surface, wherein the plurality of conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line.

3. The package substrate of claim 1 , wherein the conductive line is a transmission line, and wherein the conductive layer is a conductive reference plane.

4. The package substrate of claim 3 , wherein the transmission line is a stripline, a microstrip, a dual-stripline, or an embedded-microstrip.

5. The package substrate of claim 1 , wherein the plurality of conductive bumps have one or more shapes, and wherein the one or more shapes include rectangles, squares, circles, diamonds, or polygons, and wherein the plurality of conductive bumps have a width that is equal to a width of the conductive line.

6. The package substrate of claim 1 , wherein the conductive line includes a conductive material that is the same as a conductive material of the plurality of conductive bumps.

7. The package substrate of claim 1 , wherein the conductive line includes a thickness that is substantially equal to a thickness of the plurality of conductive bumps, or wherein the conductive line includes a thickness that is greater than a thickness of the plurality of conductive bumps.

8. The package substrate of claim 1 , wherein the plurality of conductive bumps have a first conductive bump and a second conductive bump, wherein the first conductive bump and the second conductive bump have a length, wherein the first conductive bump and the second conductive bump are separated by a gap length, and wherein the length is less than the gap length between the first and second conductive bumps.

9. A package substrate, comprising:
a dielectric over a conductive layer;
a conductive line on the dielectric;
a plurality of first conductive bumps on a top surface of the conductive line;
a plurality of first metal features on the plurality of first conductive bumps, wherein individual ones of the plurality of first metal features are on a corresponding individual one of the plurality of first conductive bumps, and wherein the plurality of first metal features has a metal conductivity different than that of the plurality of first conductive bumps;
a plurality of second conductive bumps on a bottom surface of the conductive line, wherein the plurality of first and second conductive bumps are conductively coupled to the conductive line, and wherein the plurality of second conductive bumps is embedded in the dielectric;
a plurality of second metal features on the plurality of second conductive bumps, wherein individual ones of the plurality of second metal features are on a corresponding individual one of the plurality of second conductive bumps, and wherein the plurality of second metal features has a metal conductivity different than that of the plurality of second conductive bumps; and
a solder resist over the plurality of first conductive bumps, the conductive line, and the dielectric.

10. The package substrate of claim 9 , wherein the plurality of first conductive bumps are symmetrically positioned over the plurality of second conductive bumps.

11. The package substrate of claim 9 , wherein the plurality of first conductive bumps are conductively coupled to the top surface of the conductive line, wherein the plurality of second conductive bumps are conductively coupled to the bottom surface of the conductive line, wherein the plurality of first conductive bumps are embedded in the solder resist.

12. The package substrate of claim 9 , wherein the conductive line is a transmission line, and wherein the conductive layer is a conductive reference plane.

13. The package substrate of claim 12 , wherein the transmission line is a stripline, a microstrip, a dual-stripline, or an embedded-microstrip.

14. The package substrate of claim 9 , wherein the plurality of first and second conductive bumps have one or more shapes, and wherein the one or more shapes include rectangles, squares, circles, diamonds, or polygons, and wherein the plurality of first and second conductive bumps have a width that is equal to a width of the conductive line.

15. The package substrate of claim 9 , wherein the conductive line includes a conductive material that is the same as a conductive material of the plurality of first and second conductive bumps.

16. The package substrate of claim 9 , wherein the plurality of first conductive bumps have a thickness that is substantially equal to a thickness of the plurality of second conductive bumps, or wherein the plurality of first conductive bumps have a thickness that is different than a thickness of the plurality of second conductive bumps.

17. The package substrate of claim 16 , wherein the conductive line includes a thickness that is substantially equal to the thickness of the plurality of first and second conductive bumps, or wherein the conductive line includes a thickness that is greater than the thickness of the plurality of first and second conductive bumps.

Assignees

• Intel Corp

Inventors

• Yong Khang Choong
• Ho Ying Ern
• Lim Yun Rou
• Song Wil Choon
• Hall Stephen

Classifications

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/072

  of bump connectors · CPC title