Stacked transmission line

Patent metadata

Field	Value
Publication number	US-10149377-B2
Application number	US-201615192549-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Jun 24, 2016
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A stacked, multi-layer transmission line is provided. The stacked transmission line includes at least a pair of conductive traces, each conductive trace having a plurality of conductive stubs electrically coupled thereto. The stubs are disposed in one or more separate spatial layers from the conductive traces.

First claim

What is claimed is:

1. A multi-layer microelectronic structure, comprising:
a first conductive trace disposed at a first spatial layer of a carrier or a package oriented in a first plane, the first conductive trace being coplanar to a plane of the first spatial layer and the plane of the first spatial layer being parallel to the first plane;
a second conductive trace disposed at the first spatial layer and coplanar to the first conductive trace, at least a portion of the second conductive trace parallel to the first conductive trace, the first and second conductive traces comprising a transmission line;
a first plurality of conductive stubs disposed at a second spatial layer of the carrier or the package and electrically coupled to the first conductive trace, one or more stubs of the first plurality of conductive stubs fully overlaps one or more sections of the second conductive trace in a plan view without being mechanically coupled to the second conductive trace, the second spatial layer different from the first spatial layer and parallel to the first spatial layer; and
a second plurality of conductive stubs disposed at a third spatial layer of the carrier or the package and electrically coupled to the second conductive trace, the second plurality of conductive stubs fully overlaps one or more sections of the first conductive trace in a plan view without being mechanically coupled to the first conductive trace, the third spatial layer different from the first spatial layer and parallel to the first spatial layer, the first and second pluralities of conductive stubs increasing a capacitive coupling between the first and second conductive traces.

2. The multi-layer microelectronic structure of claim 1 , wherein stubs of the first plurality of conductive stubs are disposed transverse to the first conductive trace and are at least partially overlapped by the first conductive trace, and stubs of the second plurality of conductive stubs are disposed transverse to the second conductive trace and are at least partially overlapped by the second conductive trace.

3. The multi-layer microelectronic structure of claim 2 , wherein at least a portion of individual conductive stubs of the first plurality of conductive stubs are at least partially overlapped by the second conductive trace without being mechanically coupled to the second conductive trace and at least a portion of individual conductive stubs of the second plurality of conductive stubs are at least partially overlapped by the first conductive trace without being mechanically coupled to the first conductive trace.

4. The multi-layer microelectronic structure of claim 1 , further comprising a first plurality of conductive vias electrically and mechanically coupling the first plurality of conductive stubs to the first conductive trace and a second plurality of conductive vias electrically and mechanically coupling the second plurality of conductive stubs to the second conductive trace.

5. The multi-layer microelectronic structure of claim 1 , further comprising one or more additional conductive traces disposed at the first spatial layer, at least a portion of each additional conductive trace parallel to the first and second conductive traces, and one or more additional pluralities of conductive stubs disposed at one or more other spatial layers of the carrier or the package and electrically coupled to the respective one or more additional conductive traces, the one or more other spatial layers different from the first spatial layer and parallel to the first spatial layer, and the one or more additional pluralities of conductive stubs increasing a capacitive coupling between the one or more additional conductive traces and the first or second conductive traces.

6. The multi-layer microelectronic structure of claim 1 , wherein the transmission line includes a compensating portion and a remaining portion, the first and second pluralities of conductive stubs coupled to the first and second conductive traces respectively at the compensating portion of the transmission line, the compensating portion arranged to reduce or eliminate far end crosstalk (FEXT) noise at least at the remaining portion of the transmission line.

7. The multi-layer microelectronic structure of claim 1 , wherein the first and second conductive traces comprise a differential interconnect, the first and second pluralities of conductive stubs arranged to reduce or eliminate differential far end crosstalk (FEXT) noise at the differential interconnect.

8. The multi-layer microelectronic structure of claim 1 , wherein stubs of the first plurality of conductive stubs are joined to the first conductive trace with a predetermined stub spacing and stubs of the second plurality of conductive stubs are joined to the second conductive trace with the predetermined stub spacing, the stubs of the first plurality alternating with the stubs of the second plurality along a length of the transmission line.

9. The multi-layer microelectronic structure of claim 1 , further comprising a pair of conductors comprising power or ground conductors of the carrier or the package, the pair of conductors disposed at a spatial layer other than the first spatial layer of the carrier or the package and parallel to the first spatial layer, and wherein at least one of the first or second pluralities of conductive stubs are formed within a space between the pair of conductors at the spatial layer of the pair of conductors.

10. The multi-layer microelectronic structure of claim 1 , wherein the third spatial layer comprises the second spatial layer.

11. A multi-layer microelectronic structure, comprising:
a first conductive trace disposed at a first spatial layer of a carrier or a package oriented in a first plane, the first conductive trace being coplanar to a plane of the first spatial layer and the plane of the first spatial layer being parallel to the first plane;
a second conductive trace disposed at a second spatial layer of the carrier or the package, the second conductive trace being coplanar to a plane of the second spatial layer, the second spatial layer different from the first spatial layer and the plane of the second spatial layer being parallel to the plane of the first spatial layer and parallel to the first plane, at least a portion of the second conductive trace overlapping parallel to the first conductive trace in a plan view, the first and second conductive traces comprising a transmission line;
a first plurality of conductive stubs disposed at a third spatial layer of the carrier or the package and electrically coupled to the first conductive trace, the first plurality of conductive stubs being coplanar to a plane of the third spatial layer, the third spatial layer different from the first spatial layer and the second spatial layer and the plane of the third spatial layer being parallel to the plane of the first spatial layer and parallel to the first plane, one or more stubs of the first plurality of conductive stubs fully overlaps one or more sections of the second conductive trace in a plan view without being mechanically coupled to the second conductive trace; and
a second plurality of conductive stubs disposed on a fourth spatial layer of the carrier or the package and electrically coupled to the second conductive trace, the second plurality of conductive stubs being coplanar to a plane of the fourth spatial layer, the fourth spatial layer different from the first spatial layer and the second spatial layer and the plane of the fourth spatial layer being parallel to the plane of the first spatial layer and parallel to the first plane, one or more stubs of the second plurality of conductive stubs fully overlaps one o

Assignees

• Invensas Corp

Inventors

• Huang Shaowu
• Delacruz Javier A
• Haba Belgacem

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W44/209

  Vertical interconnections, e.g. vias · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title