Micro-strip crosstalk compensation using stubs

Patent metadata

Field	Value
Publication number	US-9240621-B2
Application number	US-49086309-A
Country	US
Kind code	B2
Filing date	Jun 24, 2009
Priority date	Jun 24, 2009
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A micro-strip transmission line may include a plurality of conductors, wherein each conductor has a compensating portion and a remaining portion. The compensating portion can compensate for far-end crosstalk in the remaining portion. In one example, the compensating portion has a longitudinal section and a plurality of alternating stubs extending from lateral surfaces of the longitudinal section.

First claim

We claim:

1. An apparatus comprising:
a plurality of micro-strip conductors, each conductor having a compensating portion coupled with a remaining portion, the compensating portion including a plurality of stubs to compensate for crosstalk in the remaining portion, wherein a first stub of the plurality of stubs nearest to the remaining portion and a second stub of the plurality of stubs farthest from the remaining portion sandwich all remaining stubs of the plurality of stubs, wherein the second stub is adjacent to a stub only in a direction facing the remaining portion towards the first stub, and wherein a length of the compensating portion from the first stub to the second stub is less than a length of the remaining portion.

2. The apparatus of claim 1 , wherein the remaining portion has a substantially straight longitudinal section.

3. The apparatus of claim 1 , wherein the compensating portion is to further compensate for crosstalk induced timing jitter in the remaining portion.

4. The apparatus of claim 1 , wherein the compensating portion has a total length that is approximately equal to a total length of the remaining portion being compensated.

5. The apparatus of claim 1 , wherein the compensating portion includes:
a longitudinal section having lateral surfaces; and
a plurality of alternating stubs extending from the lateral surfaces.

6. The apparatus of claim 5 , wherein the longitudinal section and the plurality of alternating stubs have a geometry that is to provide the compensating portion with a mutual capacitance to self capacitance ratio that is greater than a mutual inductance to self inductance ratio of the compensating portion.

7. The apparatus of claim 6 , wherein a difference between the mutual capacitance to self capacitance ratio and the mutual inductance to self inductance ratio is to provide the conductor with a compensation voltage that cancels a voltage resulting from the crosstalk in the remaining portion.

8. A system comprising:
a synchronous dynamic random access memory;
a memory controller; and
a plurality of micro-strip conductors coupled to the memory and the memory controller, each conductor having a compensating portion coupled with a remaining portion, the compensating portion including a plurality of stubs to compensate for crosstalk in the remaining portion, wherein a first stub of the plurality of stubs nearest to the remaining portion and a second stub of the plurality of stubs farthest from the remaining portion sandwich all remaining stubs of the plurality of stubs, wherein the second stub is adjacent to a stub only in a direction facing the remaining portion towards the first stub, and wherein a length of the compensating portion from the first stub to the second stub is less than a length of the remaining portion.

9. The system of claim 8 , wherein the remaining portion has a substantially straight longitudinal section.

10. The system of claim 8 , wherein the compensating portion is to further compensate for crosstalk induced timing jitter in the remaining portion.

11. The system of claim 8 , further including a circuit board having an external dielectric layer coupled to the memory, the memory controller and the plurality of micro-strip conductors.

12. The system of claim 8 , wherein the circuit board further includes a ground plane coupled to the external dielectric layer.

13. The system of claim 8 , wherein the memory includes a dual data rate memory.

14. The system of claim 8 , further including a processor coupled to the memory controller.

15. The system of claim 8 , wherein the compensating portion includes:
a longitudinal section having lateral surfaces; and
a plurality of alternating stubs extending from the lateral surfaces.

16. The system of claim 15 , wherein the longitudinal section and the plurality of alternating stubs have a geometry that is to provide the compensating portion with a mutual capacitance to self capacitance ratio that is greater than a mutual inductance to self inductance ratio of the compensating portion.

17. The system of claim 16 , wherein a difference between the mutual capacitance to self capacitance ratio and the mutual inductance to self inductance ratio is to provide the conductor with a compensation voltage that cancels a voltage resulting from the crosstalk in the remaining portion.

Assignees

• Abbott John J
• Kunze Richard K
• Intel Corp

Inventors

• Abbott John J
• Kunze Richard K

Classifications

• H03H7/38

  Impedance-matching networks · CPC title

• H01P3/081 Primary

  Microstriplines · CPC title