Integrated circuit package substrate with microstrip architecture and electrically grounded surface conductive layer

Patent metadata

Field	Value
Publication number	US-9972589-B1
Application number	US-201715474293-A
Country	US
Kind code	B1
Filing date	Mar 30, 2017
Priority date	Mar 30, 2017
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Described herein are integrated circuit structures having a package substrate with microstrip architecture as the uppermost layers and a surface conductive layer that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit package substrate may have an internal ground plane, a dielectric layer, a microstrip signal layer as the top transmission line layer, a solder resist layer, and a surface conductive layer that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit package substrate may include altering thicknesses of the dielectric and/or solder resist layers to optimize electrical performance by having the microstrip signal layer closer in proximity to the internal ground layer as compared to the surface conductive layer.

First claim

The invention claimed is:

1. An integrated circuit package substrate comprising:
an internal ground layer;
a dielectric layer on the internal ground layer;
a microstrip signal layer on the dielectric layer, wherein the microstrip signal layer is the top transmission line layer;
a solder resist layer on the microstrip signal layer, wherein the solder resist layer includes a die attaching area and a non-die attaching area; and
a surface conductive layer on the solder resist layer in the non-die attaching area, wherein the surface conductive layer is electrically connected to the internal ground layer,
wherein the surface conductive layer at least partially covers the non-die attaching area on the solder resist layer.

2. The integrated circuit package substrate of claim 1 , wherein the surface conductive layer comprises one or more of copper, nickel, palladium, aluminum, silver, and gold.

3. The integrated circuit package substrate of claim 1 , wherein the surface conductive layer exhibits properties characteristic of electroless plating.

4. The integrated circuit package substrate of claim 1 ,
wherein the surface conductive layer entirely covers the non-die attaching area on the solder resist layer.

5. The integrated circuit package substrate of claim 1 , wherein the line geometry of the microstrip signal layer has a first width in a first area covered by the surface conductive layer and a second width that is different from the first width in a second area not covered by the surface conductive layer.

6. The integrated circuit package substrate of claim 5 , wherein the first width is less than the second width.

7. The integrated circuit package substrate of claim 1 , wherein one or more vias form the electrical connection between the surface conductive layer and the internal ground layer.

8. The integrated circuit package substrate of claim 1 , wherein the thickness of the solder resist layer is greater than the thickness of the dielectric layer.

9. An integrated circuit package comprising:
a package substrate, the package substrate comprising:
an internal ground layer,
a dielectric layer on the internal ground layer,
a microstrip signal layer on the dielectric layer, wherein the microstrip signal layer is the top transmission line layer;
a solder resist layer on the microstrip signal layer, wherein the solder resist layer includes a die attaching area and a non-die attaching area, and
a surface conductive layer on the solder resist layer in the non-die attaching area, wherein the surface conductive layer is electrically connected to the internal ground layer;

a die, wherein the die is attached to the package substrate in the die attaching area; and
first level interconnects, wherein the die is electrically coupled to the package substrate via the first level interconnects,
wherein the surface conductive layer at least partially covers non-die attaching area on the solder resist layer.

10. The integrated circuit package of claim 9 , wherein the surface conductive layer comprises one or more of copper, nickel, palladium, aluminum, silver, and gold.

11. The integrated circuit package of claim 9 , wherein the surface conductive layer exhibits properties characteristic of electroless plating.

12. The integrated circuit package of claim 9 , wherein the surface conductive layer entirely covers the non-die attaching area on the solder resist layer.

13. The integrated circuit package substrate of claim 9 , wherein the line geometry of the microstrip signal layer has a first width in a first area covered by the surface conductive layer and a second width that is different from the first width in a second area not covered by the surface conductive layer.

14. The integrated circuit package of claim 9 , wherein one or more vias form the electrical connection between the surface conductive layer and the internal ground layer.

15. The integrated circuit package of claim 9 , wherein the thickness of the solder resist layer is greater than the thickness of the dielectric layer.

16. A method for fabricating an integrated circuit package substrate, the method comprising:
forming an internal ground layer on a substrate on a substrate;
forming a dielectric layer on the internal ground layer;
forming a microstrip signal layer on the dielectric layer;
forming a solder resist layer on the microstrip signal layer, wherein the solder resist layer includes a die attaching area and a non-die attaching area;
forming a surface conductive layer on the solder resist layer in the non-die attaching area; and
forming an electrical connection between the surface conductive layer and the internal ground layer,
wherein the surface conductive layer at least partially covers the non-die attaching area on the solder resist layer.

17. The method of claim 16 , wherein the surface conductive layer comprises one or more of copper, nickel, palladium, aluminum, silver, and gold.

18. The method of claim 16 , wherein the surface conductive layer is deposited by electroless plating.

19. The method of claim 16 , wherein the surface conductive layer entirely covers the non-die attaching area on the solder resist layer.

20. The integrated circuit package substrate of claim 16 , wherein the line geometry of the microstrip signal layer has a first width in a first area covered by the surface conductive layer and a second width that is different from the first width in a second area not covered by the surface conductive layer.

21. The method of claim 16 , wherein one or more vias form the electrical connection between the surface conductive layer and the internal ground layer.

22. The method of claim 16 , wherein the thickness of the solder resist layer is greater than the thickness of the dielectric layer.

Assignees

• Intel Corp

Inventors

• Goh Eng Huat
• Lim Min Suet
• Sir Jiun Hann
• Lim Seok Ling
• Teoh Hoay Tien

Classifications

• H01P3/082

  Multilayer dielectric · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title