Methods for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-11949040-B2
Application number	US-202217725732-A
Country	US
Kind code	B2
Filing date	Apr 21, 2022
Priority date	Aug 1, 2017
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a plurality of diodes on a first substrate;
forming a first pattern array on a second substrate;
transferring the plurality of diodes from the first substrate to the second substrate;
forming the first pattern array on a third substrate;
transferring the plurality of diodes from the second substrate to the third substrate;
forming a second pattern array on a fourth substrate; and
transferring the plurality of diodes from the third substrate to the fourth substrate,
wherein during transferring the plurality of diodes from the third substrate to the fourth substrate, spacer layers on the third substrate are aligned with plurality of spacer layers on the fourth substrate and plurality of non-aligned spacer layers on the fourth substrate are in between aligned plurality of spacer layers on the fourth substrate and at least one of the plurality of diodes is transferred between plurality of non-aligned spacer layers on the fourth substrate,
wherein a pitch between the plurality of diodes on the first substrate is different from a pitch of the first pattern array.

2. The method as claimed in claim 1 , wherein the pitch of the first pattern array is n times larger than a pitch of the second pattern array, and wherein n is a positive integer.

3. The method as claimed in claim 1 , wherein the first pattern array comprises an adhesive layer.

4. The method as claimed in claim 1 , wherein a material of the second substrate is conductive.

5. The method as claimed in claim 1 , wherein a material of the third substrate is conductive.

Assignees

• Innolux Corp

Inventors

• Cheng Kai
• Hsieh Tsau-Hua
• Lin Fang-Ying
• Liu Tung-Kai
• Wang Hui-Chieh
• Lin Chun-Hsien
• Ko Jui-Feng

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/0198

  batch processes · CPC title

• H10H20/825

  containing nitrogen, e.g. GaN · CPC title

• H10H20/0364

  of interconnections · CPC title

• H10H20/0137

  the light-emitting regions comprising nitride materials · CPC title