Integrated circuit device

Patent metadata

Field	Value
Publication number	US-11948942-B2
Application number	US-202318122253-A
Country	US
Kind code	B2
Filing date	Mar 16, 2023
Priority date	Aug 12, 2020
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1−xGex layer, where x≠0, and the inner blocking layer including a Si layer.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a fin-type active area along a first horizontal direction on a substrate;
a nanosheet stack including at least one nanosheet on a fin top of the fin-type active area, the at least one nanosheet being spaced apart from the fin top in a vertical direction;
a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure surrounding the at least one nanosheet; and
a source/drain area on the fin-type active area, the source/drain area contacting the at least one nanosheet, and the source/drain area including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area,
wherein each of the outer blocking layer and the main body layer includes a Si 1-x Ge x layer, where x≠0, and the inner blocking layer includes a Si layer, and
wherein a level of a lowermost surface of the source/drain area is lower than a level of the fin top in the vertical direction.

2. The integrated circuit device as claimed in claim 1 , wherein:
the outer blocking layer includes a first bottom portion contacting the fin-type active area, the first bottom portion having a first thickness in the vertical direction, and
the inner blocking layer includes a second bottom portion contacting the first bottom portion of the outer blocking layer, the second bottom portion having a second thickness in the vertical direction, and the second thickness being equal to or greater than the first thickness.

3. The integrated circuit device as claimed in claim 1 , wherein a width of the outer blocking layer in the first horizontal direction is variable along the second horizontal direction.

4. The integrated circuit device as claimed in claim 1 , wherein a width of the inner blocking layer in the first horizontal direction is variable along the second horizontal direction.

5. The integrated circuit device as claimed in claim 1 , wherein the gate structure includes:
a gate line;
a gate dielectric layer surrounding the gate line; and
an outer insulating spacer spaced apart from the gate line by the gate dielectric layer, the outer insulating spacer covering opposite sidewalls of the gate line on the fin-type active area,
wherein the outer blocking layer has a first contact surface in contact with the gate structure, and
wherein the inner blocking layer has a second contact surface in contact with the gate structure, an area of the second contact surface being greater than an area of the first contact surface.

6. The integrated circuit device as claimed in claim 1 , wherein:
the gate structure includes a gate line having a main-gate portion along the second horizontal direction on the substrate and a sub-gate portion between the at least one nanosheet and the fin top, the sub-gate portion being integrally connected to the main-gate portion,
the outer blocking layer includes a first edge portion covering an end corner of the nanosheet stack that is closest to the main-gate portion,
the inner blocking layer includes a second edge portion covering the end corner of the nanosheet stack, and
a width of the second edge portion is greater than a width of the first edge portion in the first horizontal direction.

7. The integrated circuit device as claimed in claim 1 , wherein:
the outer blocking layer includes a first middle portion covering the nanosheet stack on a central portion of the fin top in the second horizontal direction,
the inner blocking layer includes a second middle portion in contact with the first middle portion, and
a width of the second middle portion in the first horizontal direction is equal to or greater than a width of the first middle portion.

8. The integrated circuit device as claimed in claim 1 , wherein the inner blocking layer includes an undoped Si layer.

9. The integrated circuit device as claimed in claim 1 , wherein the inner blocking layer includes a Si layer doped with a p-type dopant, the p-type dopant being boron (B) or gallium (Ga).

10. The integrated circuit device as claimed in claim 1 , wherein the source/drain area further includes a capping layer spaced apart from the inner blocking layer with the main body layer therebetween, and the capping layer includes an undoped Si layer or a Si layer doped with a p-type dopant.

11. An integrated circuit device, comprising:
a fin-type active area along a first horizontal direction on a substrate, the fin-type active area including a fin top and a recess, and a level of a lowermost surface of the recess being less than a level of the fin top in a vertical direction;
a nanosheet stack including a plurality of nanosheets on the fin top, the plurality of nanosheets being spaced apart from the fin top and having different vertical distances from the fin top; and
a source/drain area on the recess and facing the plurality of nanosheets in the first horizontal direction, the source/drain area including an outer blocking layer, an inner blocking layer, and a main body layer that are sequentially stacked on the nanosheet stack and on the recess,
wherein each of the outer blocking layer and the main body layer includes a Si 1-x Ge x layer, where x≠0, and the inner blocking layer includes a Si layer, and
wherein a first level of a lowermost surface of the outer blocking layer is lower than the level of the fin top in the vertical direction.

12. The integrated circuit device as claimed in claim 11 , wherein a second level of a lowermost surface of the inner blocking layer is lower than the level of the fin top in the vertical direction.

13. The integrated circuit device as claimed in claim 11 , wherein at least a portion of the inner blocking layer has a width greater than a width of the outer blocking layer in the first horizontal direction.

14. The integrated circuit device as claimed in claim 11 , wherein:
the outer blocking layer includes a first bottom portion contacting the lowermost surface of the recess, the first bottom portion having a first thickness in the vertical direction, and
the inner blocking layer includes a second bottom portion contacting the first bottom portion of the outer blocking layer, the second bottom portion having a second thickness in the vertical direction, and the second thickness being equal to or greater than the first thickness.

15. The integrated circuit device as claimed in claim 11 , wherein a width of the outer blocking layer in the first horizontal direction is variable along a second horizontal direction.

16. The integrated circuit device as claimed in claim 11 , wherein a width of the inner blocking layer in the first horizontal direction is variable along a second horizontal direction.

17. The integrated circuit device as claimed in claim 11 , further comprising:
a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure surrounding the plurality of nanosheets; and
a device isolation layer on opposite sidewalls of the fin-type active area,
wherein the gate structure includes:
a gate line along the second horizontal direction on the fin-type active area and on the device isolation layer;
a gate dielectric layer surrounding the gate line; and
an outer insulating spacer covering opposite sidewalls of the gate line on the fin-type active area and on the device isolation layer,
wherein the outer blocking layer has a first contact surface in contact with the gate structure, and
wherein the inner blocking layer has a second contact surface in contact with the gat

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Minhee
• Cho Keunhwi
• Kang Myunggil
• Kim Seokhoon
• Kim Dongwon
• Park Pankwi
• Shin Dongsuk

Classifications

• H10P14/3444

  P-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title