Integrated circuit including standard cell and filler cell

Patent metadata

Field	Value
Publication number	US-11948932-B2
Application number	US-202117528242-A
Country	US
Kind code	B2
Filing date	Nov 17, 2021
Priority date	Mar 26, 2021
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.

First claim

What is claimed is:

1. An integrated circuit comprising:
a plurality of standard cells spaced apart from each other in a first direction; and
a plurality of filler cells arranged between the plurality of standard cells,
wherein at least one of the plurality of filler cells comprises:
a first active region extending in the first direction and having a first width; and
a second active region of a different type from that of the first active region, the second active region being spaced apart from the first active region in a second direction perpendicular to the first direction and extending in the first direction, wherein at least one of the plurality of standard cells comprises:
a third active region of a same type as that of the first active region, the third active region being adjacent to the first active region in the first direction, extending in the first direction, and having a second width which is less than the first width;
a fourth active region of a same type as that of the second active region, the fourth active region being spaced apart from the third active region in the second direction and extending in the first direction; and
a first tapering portion of the same type as that of the first active region, the first tapering portion comprising a first contact surface contacting the first active region in the first direction, a second contact surface contacting the third active region in the first direction, and an inclination surface connecting the first contact surface to the second contact surface and having an inclination.

2. The integrated circuit of claim 1 ,
wherein the second active region has the first width,
wherein the fourth active region has the second width, and
wherein at least one of the plurality of standard cells comprises a second tapering portion of the same type as that of the second active region, the second tapering portion comprising a first surface contacting the second active region in the first direction, a second surface contacting the fourth active region in the first direction, and a third surface connecting the first surface to the second surface and having an inclination.

3. The integrated circuit of claim 2 , wherein a distance between the first tapering portion and the second tapering portion becomes shorter as it approaches a pillar cell adjacent to the first tapered portion and the second tapered portion among the filler cells.

4. The integrated circuit of claim 2 , wherein a distance between the first tapering portion and the second tapering portion is constant.

5. The integrated circuit of claim 1 , wherein a width of the second active region is different from the first width of the first active region.

6. The integrated circuit of claim 1 , wherein the inclination surface comprises a straight line or a curved line.

7. The integrated circuit of claim 1 , wherein the at least one of the plurality of filler cells further comprises a contact connected to at least one of the first active region and the second active region.

8. The integrated circuit of claim 1 , wherein the plurality of standard cells comprise a multi-bridge channel fin field transistor (FET) formed in the third active region and the fourth active region.

9. An integrated circuit comprising:
a filler cell comprising a first active region; and
a standard cell comprising:
a second active region of a same type as that of the first active region, the second active region being adjacent to the first active region in a first direction; and
a first tapering portion of the same type as that of the first active region, the first tapering portion comprising a first contact surface contacting the first active region, a second contact surface contacting the second active region, and an inclination surface connecting the first contact surface to the second contact surface and having an inclination,

wherein the first active region has a first width in a second direction perpendicular to the first direction,
wherein the second active region has a second width in the second direction, the second width being less than the first width, and
wherein the filler cell is a non-logic cell.

10. The integrated circuit of claim 9 ,
wherein the filler cell further comprises a third active region of a different type from that of the first active region and having the first width, the third active region being spaced apart from the first active region in the second direction,
wherein the standard cell further comprises:
a fourth active region of the same type as that of the third active region and having the second width, the fourth active region being spaced apart from the second active region in the first direction, and
a second tapering portion of the same type as that of the third active region, the second tapering portion comprising a first surface contacting the third active region in the first direction, a second surface contacting the fourth active region in the first direction, and a third surface connecting the first surface to the second surface and having an inclination.

11. The integrated circuit of claim 9 ,
wherein the inclination surface is a single continuous surface, and
wherein a width in the second direction of the first tapering portion decreases from the first width to the second width.

12. The integrated circuit of claim 9 , wherein a size of the first tapering portion varies depending on a width of the first active region and a width of the second active region.

13. The integrated circuit of claim 9 , wherein the inclination surface comprises a straight line or a curved line.

14. The integrated circuit of claim 9 , wherein the filler cell further comprises a contact connected to the second active region.

15. The integrated circuit of claim 9 , wherein the standard cell further comprises a gate-all-around transistor formed in the first active region.

16. An integrated circuit comprising:
a filler cell comprising a first active region; and
a standard cell comprising a second active region of a same type as that of the first active region, the second active region being adjacent to the first active region in a first direction,
wherein the standard cell further comprises a first tapering portion of the same type as that of the first active region, the first tapering portion contacting the first active region and the second active region and including an inclination surface extending from the first active region to the second active region and having an inclination,
wherein the first active region has a first width in a second direction perpendicular to the first direction and the second active region has a second width in the second direction,
wherein the first tapering portion has a width in the second direction that varies from the first width to the second width,
wherein the inclination surface is a single continuous surface, and
wherein the filler cell is a non-logic cell.

17. The integrated circuit of claim 16 ,
wherein the filler cell further comprises a third active region of a different type from that of the first active region and having the first width, the third active region being spaced apart from the first active region in the second direction,
wherein the standard cell further comprises:
a fourth active region of the same type as that of the third active region and having the second width, the fourth active region being spaced apart from the second active region in the first direction, and
a second tapering portion of the same type as that of the third active region, the second tapering portion contacting the third

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Hakchul
• Kim Ingyum
• Yang Giyoung
• Seo Jaewoo

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D84/907

  CMOS gate arrays · CPC title