Semiconductor chip package and method of assembly

Patent metadata

Field	Value
Publication number	US-11948878-B2
Application number	US-202217940125-A
Country	US
Kind code	B2
Filing date	Sep 8, 2022
Priority date	Jan 28, 2020
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

A semiconductor device substrate assembly may include a first substrate, comprising: a first insulator plate; and a first patterned metal layer, disposed on the first insulator plate, wherein the first insulator plate comprises a first material and a first thickness. The assembly may include a second substrate, comprising: a second insulator plate; and a second patterned metal layer, disposed on the second insulator plate, wherein the second insulator plate comprises the first material and the first thickness. The assembly may also include a third substrate, disposed between the first substrate and the second substrate, comprising: a third insulator plate; and a third patterned metal layer, disposed on the third insulator plate, wherein the third insulator plate comprises a second material and a second thickness, wherein at least one of the second material and the second thickness differs from the first material and the first thickness, respectively.

First claim

What is claimed is:

1. A method of forming a semiconductor package, comprising:
affixing a first substrate on a baseplate, the first substrate comprising a first insulator material, and a first patterned metal layer;
affixing a second substrate on the baseplate, the second substrate comprising the first insulator material and a second patterned metal layer; and
affixing, between the first substrate and the second substrate, a third substrate on the baseplate, the third substrate comprising a second insulator material different from the first insulator material, and further comprising a third patterned metal layer.

2. The method of claim 1 , further comprising:
affixing a first plurality of semiconductor chips on the first patterned metal layer; and
affixing a second plurality of semiconductor chips on the second patterned metal layer.

3. The method of claim 1 , further comprising connecting a busbar to the third patterned metal layer.

4. The method of claim 3 , wherein the connecting a busbar to the third patterned metal layer comprises welding the busbar to the third patterned metal layer before the affixing the third substrate to the baseplate.

5. The method of claim 3 , wherein the connecting a busbar to the third patterned metal layer comprises ultrasonic welding the busbar to the third patterned metal layer.

6. The method of claim 1 , wherein the first substrate comprises a first thickness, and wherein the second substrate comprises the first thickness.

7. The method of claim 6 , wherein the third substrate comprises a second thickness, different from the first thickness.

8. The method of claim 7 , wherein the second thickness is greater than the first thickness.

9. The method of claim 1 , wherein the first substrate and the second substrate comprise a first thermal conductivity, and the third substrate comprises a second thermal conductivity, less than the first thermal conductivity.

10. The method of claim 1 , the first insulator material comprising silicon nitride or aluminum nitride, and the second insulator material comprising aluminum nitride or aluminum oxide.

11. The method of claim 1 , wherein the first patterned metal layer and the second patterned metal layer comprise a first layer thickness, and wherein the third patterned metal layer comprises a second layer thickness, different from the first layer thickness.

12. The method of claim 1 , further comprising:
affixing a fourth substrate to the baseplate, adjacent the first substrate, on a first side of the third substrate; and
affixing a fifth substrate to the baseplate, adjacent the second substrate, on a second side of the third substrate.

13. The method of claim 3 , further comprising:
electrically connecting the third patterned metal layer to the first patterned metal layer using a first set of connectors; and
electrically connecting the third patterned metal layer to the second patterned metal layer using a second set of connectors.

14. The method of claim 2 , wherein the first plurality of semiconductor chips and the second plurality of semiconductor chips comprise a set of power semiconductor devices.

15. The method of claim 1 , wherein the affixing the first substrate, the second substrate, and the third substrate on the base plate is performed by soldering.

16. The method of claim 1 , the third substrate having mechanical properties that are more robust against a mechanical stress during the connecting the busbar to the third patterned metal layer.

Assignees

• Littelfuse Inc

Inventors

• Steinhoff Stefan

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/023

  Connecting or disconnecting interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W72/075

  of bond wires · CPC title