Semiconductor Packages and Methods of Forming the Same

Patent metadata

Field	Value
Publication number	US-2016233203-A1
Application number	US-201615131821-A
Country	US
Kind code	A1
Filing date	Apr 18, 2016
Priority date	Mar 21, 2014
Publication date	Aug 11, 2016
Grant date	—

Abstract

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

First claim

What is claimed is:

1 . A method comprising:
forming a first die package over a first carrier substrate, the first die package comprising a first die and a first electrical connector; forming redistribution layer over a second carrier substrate, the redistribution layer comprising one or more metal layers disposed in one or more passivation layers; removing the second carrier substrate from the redistribution layer to expose a first passivation layer of the one or more passivation layers; forming openings in the first passivation layer to expose portions of a first metal layer of the one or more metal layers; forming a first set of bonding structures in the openings in the first passivation layer, the first set of bonding structures being electrically coupled to the first metal layer; and bonding the redistribution layer to the first die package using the first set of bonding structures to form a first set of bonding joints, at least one of the first set of bonding joints being bonded to the first die of the first die package and at least another one of the first set of bonding joints being bonded to the first electrical connector.

2 . The method of claim 1 , wherein forming a first die package further comprises:
forming a first dielectric layer over the first carrier substrate; forming the first electrical connector over the first dielectric layer, the first electrical connector extending from a first side of the first dielectric layer; mounting the first die to the first side of the first dielectric layer; and encapsulating the first die and the first electrical connector with a molding material, the first electrical connector extending through the molding material.

3 . The method of claim 2 , further comprising:
removing the first die package from the first carrier substrate to expose a second side of the first dielectric layer, the second side being opposite the first side; forming openings from the second side of the first dielectric layer to expose portions of the first die and the first electrical connector; and bonding a second package to the first die package using a first set of conductive connectors, the first set of conductive connectors extending through the openings in the first dielectric layer.

4 . The method of claim 1 , wherein the forming the first set of bonding structures in the openings in the first passivation layer further comprises:
forming a micro bump, a solder ball, solder paste, or a combination thereof in the openings in the first passivation layer.

5 . A method comprising:
forming redistribution layer over a first carrier substrate, the redistribution layer comprising one or more metal layers disposed in one or more passivation layers; after forming the redistribution layer, attaching the redistribution layer to a second carrier substrate, the redistribution layer being interposed between the first carrier substrate and the second carrier substrate; removing the first carrier substrate to expose an exposed surface of the redistribution layer; and bonding the exposed surface of the redistribution layer to a semiconductor structure.

6 . The method of claim 5 , further comprising forming solder connections on the redistribution layer prior to attaching the redistribution layer to the second carrier substrate.

7 . The method of claim 5 , wherein the semiconductor structure comprises a packaged die, the packaged die comprising an integrated circuit die with molding compound extending along sidewalls of the integrated circuit die.

8 . The method of claim 7 , further comprising forming through vias extending through the molding compound.

9 . The method of claim 5 , wherein the bonding forms an integrated fan-out structure.

10 . The method of claim 5 , further comprising:
forming a first passivation layer over the first carrier substrate, wherein the redistribution layer is formed on the first passivation layer; after removing the first carrier substrate, forming openings in the first passivation layer to expose portions of a first metal layer of the one or more metal layers; and forming a first set of bonding structures in the openings in the first passivation layer, the first set of bonding structures being electrically coupled to the first metal layer.

11 . The method of claim 10 , wherein the bonding structures are bonded directly to corresponding contacts on the semiconductor structure.

12 . The method of claim 5 , further comprising
forming a dielectric layer over a third carrier substrate; placing a semiconductor die on the dielectric layer; encapsulating the semiconductor die, thereby forming the semiconductor structure; and after bonding the exposed surface of the redistribution layer to the semiconductor structure, removing the third carrier substrate.

13 . The method of claim 12 , further comprising forming openings in the dielectric layer and forming bump structures in the openings.

14 . A method comprising:
forming a first passivation layer over a first carrier substrate; forming redistribution layer over the first passivation layer, the redistribution layer comprising one or more metal layers disposed in one or more second passivation layers; attaching the redistribution layer to a second carrier substrate; removing the first carrier substrate from the first passivation layer; forming openings in the first passivation layer to expose portions of a first metal layer of the one or more metal layers; forming first conductive structures in the openings in the first passivation layer, the first conductive structures being electrically coupled to the first metal layer; and bonding the redistribution layer to a first die package.

15 . The method of claim 14 , further comprising forming the first die package over a third carrier substrate, the first die package comprising a first integrated circuit die, a first electrical connector, and an encapsulant between the first integrated circuit die and the first electrical connector.

16 . The method of claim 15 , wherein the bonding comprises directly bonding the first electrical connector to the first conductive structures.

17 . The method of claim 15 , further comprising, after the bonding, removing the third carrier substrate.

18 . The method of claim 14 , further comprising:
forming a dielectric layer on a third carrier substrate; forming the first die package on the dielectric layer; after bonding the first die package to the redistribution layer, removing the third carrier substrate; and after removing the third carrier substrate, forming electrical connections on the first die package, the electrical connections extending through the dielectric layer, the first die package being interposed between the electrical connections and the redistribution layer.

19 . The method of claim 14 , wherein a conductive structure of the redistribution layer is directly bonded to a conductive structure of the first die package.

20 . The method of claim 14 , wherein a conductive structure of the redistribution layer is solder bonded to a conductive structure of the first die package.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hsien-Wei
• Chen Jie

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title