Apparatus with multi-wafer based device and method for forming such

Patent metadata

Field	Value
Publication number	US-11948831-B2
Application number	US-202117322742-A
Country	US
Kind code	B2
Filing date	May 17, 2021
Priority date	Mar 30, 2017
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

First claim

We claim:

1. An apparatus comprising:
a first silicon section comprising one or more layers including active devices and metal layers from metal layer 0 to metal layer x, wherein x is a number greater than zero, wherein metal layer x is thicker than metal layer 0;
a second silicon section comprising one or more layers including metal layers from metal layer x+1 to metal layer y, wherein y is greater than x+1, wherein metal layer y is thicker than metal layer x+1, wherein metal layer x+1 is thicker than metal layer x; and
a layer between the first silicon section and the second silicon section, wherein the layer is configured to bond the first silicon section to the second silicon section.

2. The apparatus of claim 1 , wherein the layer is configured to bond the first silicon section to the second silicon section such that metal layer x+1 is a next metal layer over metal layer x.

3. The apparatus of claim 1 , wherein the layer includes metal.

4. The apparatus of claim 3 , wherein the metal includes one of: Cu, Ni, Co, W, or Al.

5. The apparatus of claim 1 , wherein the layer includes a dielectric.

6. The apparatus of claim 5 , wherein the dielectric includes one of: oxygen, carbon-doped oxide, polymer, or glue.

7. The apparatus of claim 1 , wherein the first silicon section includes a substrate, and the active devices are over the substrate.

8. The apparatus of claim 7 , wherein the substrate includes bulk silicon or silicon-on-insulator (SOI).

9. The apparatus of claim 8 , wherein the bulk silicon includes device quality Epi.

10. The apparatus of claim 1 , wherein the first silicon section corresponds to a first process technology node, and the second silicon section corresponds to a second process technology node different from the first process technology node.

11. The apparatus of claim 10 , wherein the first process technology node is more advanced than the second process technology node.

12. The apparatus of claim 1 , wherein the first set of one or more layers have a material formed using a first temperature, and wherein the second set of one or more layers have a material formed using a second temperature which is different than the first temperature.

13. The apparatus of claim 12 , wherein the second temperature is higher than the first temperature.

14. An apparatus comprising:
a first set of one or more layers of a first wafer including an active device and first one or more vias, wherein the first set of one or more layers and the active device comprise a first material formed using a first temperature;
a second set of one or more layers of a second wafer including second one or more vias, wherein the second set of one or more layers comprises a second material formed using a second temperature different from the first temperature; and
a layer between the first wafer and the second wafer, wherein the layer is configured to bond the first wafer to the second wafer;
wherein the first one or more vias and the second one or more vias at least partially overlap with one another at the layer that bonds the first wafer to the second wafer.

15. The apparatus of claim 14 , wherein the second temperature is higher than the first temperature.

16. The apparatus of claim 14 , wherein the first set of one or more layers correspond to a first process technology node, and wherein the second set of one or more layers correspond to a second process technology node different from the first process technology node.

17. The apparatus of claim 16 , wherein the first process technology node is more advanced than the second process technology node.

18. The apparatus of claim 14 , wherein:
the first set of one or more layers include metal layers from metal layer 0 to metal layer x, wherein x is a number greater than zero, wherein metal layer x is thicker than metal layer 0; and
the second set of one or more layers include metal layers from metal layer x+1 to metal layer y, wherein y is greater than x+1, wherein metal layer y is thicker than metal layer x+1, and wherein metal layer x+1 is thicker than metal layer x.

19. The apparatus of claim 18 , wherein the layer is configured to bond the first wafer to the second wafer such that metal layer x+1 is a next metal layer over metal layer x.

20. A system comprising:
a memory to store instructions;
a processor circuitry coupled to the memory, wherein the processor circuitry is configured to execute the instructions; and
a wireless interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes:
a first set of one or more layers of a first wafer including an active device and first one or more vias, wherein the first set of one or more layers and the active device comprise a first material formed using a first temperature;
a second set of one or more layers of a second wafer including second one or more vias, wherein the second set of one or more layers comprises a second material formed using a second temperature different from the first temperature; and
a layer between the first wafer and the second wafer, wherein the layer is configured to bond the first wafer to the second wafer;
wherein the first one or more vias and the second one or more vias are substantially aligned with respect to one another at the layer that bonds the first wafer to the second wafer.

21. The system of claim 20 , wherein the first set of one or more layers correspond to a first process technology node, and wherein the second set of one or more layers correspond to a second process technology node different from the first process technology node.

22. The system of claim 21 , wherein the first process technology node is more advanced than the second process technology node.

23. The system of claim 20 , wherein:
the first set of one or more layers include metal layers from metal layer 0 to metal layer x, wherein x is a number greater than zero, wherein metal layer x is thicker than metal layer 0; and
the second set of one or more layers include metal layers from metal layer x+1 to metal layer y, wherein y is greater than x+1, wherein metal layer y is thicker than metal layer x+1, wherein metal layer x+1 is thicker than metal layer x.

24. The system of claim 23 , wherein metal layer x is closer to the active device than to package bumps, and wherein metal layer y is closer to the package bumps than to the active device.

25. The system of claim 23 , wherein the layer is configured to bond the first wafer to the second wafer such that metal layer x+1 is a next metal layer over metal layer x.

Assignees

• Intel Corp

Inventors

• Pancholi Anup
• Majhi Prashant
• Fischer Paul
• Morrow Patrick

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10P90/1914 Primary

  using bonding · CPC title