Apparatus with multi-wafer based device and method for forming such

Patent metadata

Field	Value
Publication number	US-11037817-B2
Application number	US-201716475084-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Mar 30, 2017
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

First claim

We claim:

1. An apparatus comprising:
a substrate;
one or more active devices adjacent to the substrate;
a first set of one or more layers to interconnect the one or more active devices, wherein the one or more layers of the first set includes a first layer of a first thickness and a second layer of a second thickness greater than the first thickness, wherein the first layer is closer to the substrate than the second layer;
a second set of one or more layers, wherein the one or more layers of the second set includes a third layer of a third thickness and a fourth layer of fourth thickness greater than the third thickness; and
a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets, wherein the layer to bond includes a metal, wherein the third layer is closer to the layer to bond than the fourth layer, and wherein the second layer is closer to the layer to bond than the first layer.

2. The apparatus of claim 1 , wherein the substrate, the one or more active devices, and the first set of one of more layers are on a first wafer, and wherein the second set of one or more layers is on a second wafer.

3. The apparatus of claim 2 , wherein the substrate includes one of: bulk silicon or silicon-on-insulator (SOI).

4. The apparatus of claim 3 , wherein the bulk silicon includes device quality Epi.

5. The apparatus of claim 1 , wherein the metal includes one of: Cu, Ni, Co, W, or Al.

6. A method comprising:
forming a substrate;
forming one or more active devices adjacent to the substrate;
forming a first set of one or more layers to interconnect the one or more active devices;
forming a second set of one or more layers;
forming a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets, wherein the substrate, the one or more active devices, and the first set of one or more layers are on a first wafer, and wherein the second set of one or more layers is on a second wafer;
dry etching a surface of the second wafer such that pads are exposed; and
forming solder bumps on the exposed pads.

7. The method of claim 6 , wherein the substrate includes one of: bulk silicon or silicon-on-insulator (SOI).

8. The method of claim 7 , wherein the bulk silicon includes device quality Epi.

9. The method of claim 6 , wherein the layer to bond includes at least one of a dielectric or a metal.

10. The method of claim 9 , wherein the dielectric includes one of: oxygen, carbon-doped oxide, polymer, or glue.

11. The method of claim 9 , wherein the metal includes one of: Cu, Ni, Co, W, or Al.

12. A system comprising: a memory; a processor coupled to the memory, the processor having an apparatus which includes:
a substrate;
one or more active devices adjacent to the substrate;
a first set of one or more layers to interconnect the one or more active devices wherein the one or more layers of the first set includes a first layer of a first thickness and a second layer of a second thickness greater than the first thickness, wherein the first layer is closer to the substrate than the second layer;
a second set of one or more layers, wherein the one or more layers of the second set includes a third layer of a third thickness and a fourth layer of fourth thickness greater than the third thickness; and
a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets, wherein the layer to bond includes a metal, wherein the third layer is closer to the layer to bond than the fourth layer, and wherein the second layer is closer to the layer to bond than the first layer; and
a wireless interface to allow the processor to communicate with another device.

13. The system of claim 12 , wherein the substrate, the one or more active devices, and the first set of one of more layers are on a first wafer, and wherein the second set of one or more layers is on a second wafer.

14. The system of claim 13 , wherein the substrate includes one of: bulk silicon or silicon-on-insulator (SOI).

15. The system of claim 14 , wherein the bulk silicon includes device quality Epi.

16. The system of claim 12 , wherein the metal includes one of: Cu, Ni, Co, W, or Al.

Assignees

• Intel Corp

Inventors

• Pancholi Anup
• Majhi Prashant
• Fischer Paul
• Morrow Patrick

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10P90/1914 Primary

  using bonding · CPC title