Wafer-to-wafer bonding structure

Patent metadata

Field	Value
Publication number	US-2016013160-A1
Application number	US-201514796506-A
Country	US
Kind code	A1
Filing date	Jul 10, 2015
Priority date	Jul 11, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

First claim

What is claimed is:

1 . A wafer-to-wafer bonding structure comprising:
a first wafer comprising a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer comprising a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer on protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

2 . The wafer-to-wafer bonding structure of claim 1 , wherein the polymer layer comprises a first polymer layer on the first wafer and a second polymer layer on the second wafer that are bonded to each other.

3 . The wafer-to-wafer bonding structure of claim 1 , wherein the polymer layer comprises at least one material selected from the group consisting of polyimide, polyamide, polyacrylate, and polyaramide.

4 . The wafer-to-wafer bonding structure of claim 1 , wherein the polymer layer has a hardness of 90% or above.

5 . The wafer-to-wafer bonding structure of claim 1 , wherein the polymer layer is on edges and/or bevel areas, between the first and second wafers.

6 . The wafer-to-wafer bonding structure of claim 1 ,
wherein the first wafer comprises a first multilayer wiring structure on the first substrate and the second wafer comprises a second multilayer wiring structure on the second substrate, wherein the first insulating layer is on the first multilayer wiring structure, and the second insulating layer is on the second multilayer wiring structure, and wherein the first Cu pad is electrically connected to the first multilayer wiring structure, and the second Cu pad is electrically connected to the second multilayer wiring structure.

7 . The wafer-to-wafer bonding structure of claim 1 , wherein the first and second insulating layers respectively comprise a multilayer structure comprising one or more alternately stacked nitride layers and oxide layers.

8 . The wafer-to-wafer bonding structure of claim 1 , wherein at least one of the first and second insulating layers comprises a first silicon carbon nitride (SiCN) layer, a first tetraethyl orthosilicate (TEOS) layer, and a second SiCN layer that are sequentially stacked.

9 . The wafer-to-wafer bonding structure of claim 8 , wherein the at least one of the first and second insulating layers further comprises a second TEOS layer on the second SiCN layer.

10 . The wafer-to-wafer bonding structure of claim 1 ,
wherein the first Cu pad comprises a first upper Cu pad and a first lower Cu pad, wherein the second Cu pad comprises a second upper Cu pad and a second lower Cu pad, wherein the first barrier metal layer comprises a first lower barrier metal layer on a lower surface and sides of the first lower Cu pad and a first upper barrier metal layer on a lower surface and sides of the first upper Cu pad, and wherein the second barrier metal layer comprises a second lower barrier metal layer on a lower surface and sides of the second lower Cu pad and a second upper barrier metal layer on a lower surface and sides of the second upper Cu pad.

11 . The wafer-to-wafer bonding structure of claim 10 , wherein the polymer layer is on portions of sides of the first and second upper barrier metal layers.

12 . A wafer-to-wafer bonding structure comprising:
a first substrate; a first multilayer wiring structure on the first substrate; a first insulating layer on the first multilayer wiring structure; a polymer layer on the first insulating layer; a second insulating layer on the polymer layer; a second multilayer wiring structure on the second insulating layer; a second substrate on the second multilayer wiring structure; a copper (Cu) pad that penetrates the first insulating layer, the polymer layer, and the second insulating layer; and barrier metal layers between the Cu pad and the first insulating layer, the polymer layer, and the second insulating layer.

13 . The wafer-to-wafer bonding structure of claim 12 ,
wherein sides of the barrier metal layers are on sides of the Cu pad, and wherein the polymer layer is on portions of the sides of the barrier metal layers.

14 . The wafer-to-wafer bonding structure of claim 12 ,
wherein the barrier metal layers are on lower and upper surfaces of the Cu pad, and wherein the Cu pad is electrically connected to the first multilayer wiring structure through a first of the barrier metal layers on the lower surface of the Cu pad and is electrically connected to the second multilayer wiring structure through the a second of the barrier metal layers on the upper surface of the Cu pad.

15 . The wafer-to-wafer bonding structure of claim 12 ,
wherein the Cu pad comprises a lower Cu pad having a first width, an intermediate Cu pad having a second width, and an upper Cu pad having a third width, wherein the barrier metal layers comprise a lower barrier metal layer on portions of the lower Cu pad, intermediate barrier metal layers on portions of the intermediate Cu pad, and an upper barrier metal layer on portions of the upper Cu pad, and wherein the polymer layer is on the intermediate barrier metal layers on portions of sides of the intermediate Cu pad.

16 . A wafer-to-wafer bonding structure comprising:
a first substrate; a first interlayer insulating layer on the first substrate and comprising a first wiring structure; a first nitride layer on the first interlayer insulating layer; a first oxide layer on the first nitride layer; a second nitride layer on the first oxide layer; a polymer layer on the second nitride layer and configured to provide a bonding force; a third nitride layer on the polymer layer; a second oxide layer on the third nitride layer; a fourth nitride layer on the second oxide layer; a second interlayer insulating layer on the fourth nitride layer and comprising a second wiring structure; a second substrate on the second interlayer insulating layer; a copper (Cu) pad extending within the second nitride layer, the polymer, layer, and the third nitride layer and electrically connected to the first wiring structure and the second wiring structure; and a barrier metal layer between the Cu pad and the second nitride layer, the polymer, layer, and the third nitride layer.

17 . The wafer-to-wafer bonding structure of claim 16 wherein the polymer layer comprises a polymer that is configured to bond to another polymer layer, reflow, and crystallize at a temperature of a copper bonding thermal treatment.

18 . The wafer-to-wafer bonding structure of claim 16 , further comprising:
a third oxide layer between the second nitride layer and the polymer layer; and a fourth oxide layer between the polymer layer and the third nitride layer, wherein a bottom surface of the Cu pad is within the first oxide layer, and wherein a top surface of the Cu pad is within the second oxide layer.

19 . The wafer-to-wafer bonding structure of claim 16 ,
wherein the Cu pad comprises a first portion comprising a first width within the polymer layer, a second portion comprising a second width smaller than the first width between the firs

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chun Jin-Ho
• Kang Pil-Kyu
• Park Byung-Iyul
• Park Jae-Hwa
• Choi Ju-Il

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title