Imaging device operated by switching between product-sum operation

Patent metadata

Field	Value
Publication number	US-11943554-B2
Application number	US-202017605817-A
Country	US
Kind code	B2
Filing date	Apr 14, 2020
Priority date	Apr 29, 2019
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

An imaging device capable of executing image processing is provided. Analog data (image data) acquired through an imaging operation is retained in a pixel, and data obtained by multiplying the analog data by a given weight coefficient in the pixel can be extracted. The data is taken into a neural network or the like, whereby processing such as image recognition can be performed. Since an enormous amount of image data can be retained in pixels in an analog data state, processing can be performed efficiently.

First claim

The invention claimed is:

1. An imaging device comprising a pixel block, a first circuit, and a second circuit,
wherein the pixel block comprises a plurality of pixels arranged in a matrix,
wherein the plurality of pixels are electrically connected to the second circuit,
wherein the first circuit has a function of selecting pixels arranged in one row of the plurality of pixels,
wherein the first circuit has a function of selecting pixels arranged in a plurality of consecutive rows of the plurality of pixels,
wherein the first circuit has a function of changing the number of rows to be selected,
wherein the pixel has a function of generating first data,
wherein the pixel has a function of generating second data by adding a predetermined potential to the first data,
wherein the second circuit has a function of generating third data corresponding to a sum of the first data generated by the plurality of pixels,
wherein the second circuit generates fourth data by adding, to the third data, a potential corresponding to a sum of the second data generated by the plurality of pixels
wherein the first circuit is a shift register circuit comprising a first logic circuit, a second logic circuit, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor,
wherein an output terminal of the first logic circuit is electrically connected to one of a source and a drain of the twelfth transistor,
wherein an output terminal of the second logic circuit is electrically connected to one of a source and a drain of the thirteenth transistor,
wherein the other of the source and the drain of the twelfth transistor is electrically connected to one of a source and a drain of the fourteenth transistor,
wherein the other of the source and the drain of the fourteenth transistor is electrically connected to the other of the source and the drain of the thirteenth transistor,
wherein the other of the source and the drain of the twelfth transistor is electrically connected to one of a source and a drain of the fifteenth transistor, and
wherein the other of the source and the drain of the fifteenth transistor is electrically connected to a power supply line.

2. The imaging device according to claim 1 ,
wherein the pixel comprises a photoelectric conversion device, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a first capacitor,
wherein one electrode of the photoelectric conversion device is electrically connected to one of a source and a drain of the first transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the second transistor is electrically connected to a gate of the third transistor,
wherein the gate of the third transistor is electrically connected to one electrode of the first capacitor,
wherein the other electrode of the first capacitor is electrically connected to one of a source and a drain of the fourth transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the second circuit, and
wherein a gate of the fifth transistor is electrically connected to the first circuit.

3. The imaging device according to claim 2 ,
wherein the photoelectric conversion device is provided in a first layer,
wherein the transistors included in the pixel block and the first circuit are provided in a second layer,
wherein the transistors included in the second circuit are provided in a third layer,
wherein the second layer is provided between the first layer and the third layer,
wherein the first layer to the third layer comprise an overlap region, and
wherein at least the first layer and the second layer, or the second layer and the third layer are attached to each other in a bonding step.

4. The imaging device according to claim 3 , further comprising a fourth layer,
wherein the fourth layer comprises a transistor that is a component of a circuit included in the third layer,
wherein the fourth layer is provided between the second layer and the third layer,
wherein the first layer to the fourth layer comprise an overlap region, and
wherein the second layer and the fourth layer are attached to each other in a bonding step.

5. The imaging device according to claim 4 ,
wherein the transistor included in the fourth layer comprises a metal oxide in a channel formation region, and the metal oxide comprises In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

6. The imaging device according to claim 1 ,
wherein the second circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a second capacitor, and a resistor,
wherein one electrode of the second capacitor is electrically connected to the plurality of pixels,
wherein the one electrode of the second capacitor is electrically connected to the resistor,
wherein the other electrode of the second capacitor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the one of the source and the drain of the sixth transistor is electrically connected to a gate of the seventh transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor, and
wherein the one of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor.

7. The imaging device according to claim 1 , further comprising a third circuit,
wherein the pixel further comprises a tenth transistor and an eleventh transistor,
wherein the third circuit has a structure and a function equivalent to those of the second circuit,
wherein a gate of the tenth transistor is electrically connected to a gate of a third transistor,
wherein one of a source and a drain of the tenth transistor is electrically connected to one of a source and a drain of the eleventh transistor,
wherein the other of the source and the drain of the eleventh transistor is electrically connected to the third circuit, and
wherein a gate of the eleventh transistor is electrically connected to the first circuit.

8. The imaging device according to claim 1 ,
wherein the transistors included in the pixel block and the first circuit each comprise a metal oxide in a channel formation region, and the metal oxide comprises In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).

9. The imaging device according to claim 1 ,
wherein the transistors included in the pixel block, the first circuit, and the second circuit each comprise silicon in a channel formation region.

10. An electronic device comprising a display device and the imaging device according to claim 1 .

11. The imaging device according to claim 1 ,
wherein the second circuit is provided outside of the pixel block.

Assignees

• Semiconductor Energy Lab

Inventors

• Yoneda Seiichi
• Negoro Yusuke
• Kobayashi Hidetomo

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D30/674

  characterised by the active materials · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title