Semiconductor package including a through-electrode penetrating a molding part

Patent metadata

Field	Value
Publication number	US-11942458-B2
Application number	US-202117511178-A
Country	US
Kind code	B2
Filing date	Oct 26, 2021
Priority date	Feb 16, 2021
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

A semiconductor package includes a first substrate, a first semiconductor chip and a passive device which are laterally spaced apart from each other on the first substrate and are disposed face-up on the first substrate, a first molding part surrounding the first semiconductor chip and the passive device on the first substrate, a second semiconductor chip disposed on the first molding part and electrically connected to the first semiconductor chip and the passive device, a second molding part surrounding the second semiconductor chip on the first molding part, first through-electrodes vertically penetrating the first molding part, at least some of first through-electrodes electrically connect the first substrate to the second semiconductor chip, and external terminals provided under the first substrate.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first substrate;
a first semiconductor chip and a passive device which are laterally spaced apart from each other on the first substrate and are disposed face-up on the first substrate;
a first molding part surrounding the first semiconductor chip and the passive device on the first substrate;
a second semiconductor chip disposed on the first molding part and electrically connected to the first semiconductor chip and the passive device;
a second molding part surrounding the second semiconductor chip on the first molding part;
first through-electrodes vertically penetrating the first molding part, at least some of first through-electrodes electrically connecting the first substrate to the second semiconductor chip;
external terminals provided under the first substrate,
wherein the first semiconductor chip comprises:
a base layer;
a circuit layer provided on a top surface of the base layer, the top surface of the base layer facing the second semiconductor chip; and
a via penetrating the base layer to be electrically connected to the circuit layer,
a solder bump connecting the via to the first substrate; and
an adhesive film adhering an inactive surface of the passive device to the first substrate.

2. The semiconductor package of claim 1 , wherein the second semiconductor chip vertically overlaps the whole of the first semiconductor chip and the whole of the passive device.

3. The semiconductor package of claim 1 , further comprising:
a redistribution layer disposed between the first molding part and the second molding part,
wherein the second semiconductor chip is mounted on a top surface of the redistribution layer by using first connection terminals, and
wherein the first semiconductor chip and the passive device are mounted on a bottom surface of the redistribution layer through chip bumps.

4. The semiconductor package of claim 3 , wherein a first sub-through-electrode of the first through-electrodes is provided between the first semiconductor chip and the passive device,
wherein a second sub-through-electrode of the first through-electrodes is provided outside the second semiconductor chip in a plan view, and
wherein the second semiconductor chip is electrically connected to the first substrate through the redistribution layer and the first sub-through-electrode.

5. The semiconductor package of claim 3 , further comprising:
a second through-electrode vertically penetrating the second molding part; and
a second substrate provided on the second molding part and electrically connected to the second through-electrode,
wherein a second sub-through-electrode of the first through-electrodes is disposed at a side of the first semiconductor chip or at a side of the passive device, and
wherein the second through-electrode is electrically connected to the first substrate through the redistribution layer and the second sub-through-electrode.

6. The semiconductor package of claim 1 , further comprising:
first pads provided on a top surface of the first molding part and electrically connected to the circuit layer of the first semiconductor chip; and
second pads provided on the top surface of the first molding part and electrically connected to the passive device,
wherein the second semiconductor chip is mounted on the first and second pads.

7. The semiconductor package of claim 6 , further comprising:
an intermediate insulating layer provided between the first molding part and the second molding part,
wherein the intermediate insulating layer surrounds the first and second pads.

8. The semiconductor package of claim 6 , wherein the second semiconductor chip is mounted on the first and second pads by using first connection terminals provided between the first pads and some of chip pads provided on a bottom surface of the second semiconductor chip and between the second pads and others of the chip pads.

9. The semiconductor package of claim 1 , wherein the first molding part is in contact with the second molding part,
wherein the first semiconductor chip and the passive device are embedded in the first molding part,
wherein each of the first semiconductor chip and the passive device have bumps exposed at a top surface of the first molding part, and
wherein the second semiconductor chip is electrically connected to the exposed bumps.

10. The semiconductor package of claim 9 , wherein the second semiconductor chip has chip pads provided on a bottom surface of the second semiconductor chip, and the chip pads contact the bumps.

11. The semiconductor package of claim 1 , wherein the first semiconductor chip is electrically connected to the first substrate by using a second connection terminal, the second connection terminal is provided on a bottom surface of the first semiconductor chip to be directly connected to the via.

12. A semiconductor package comprising:
a first substrate;
a first device and a second device spaced apart from each other on the first substrate;
a third device disposed on the first device and the second device, wherein a first active surface of the first device and a second active surface of the second device face a third active surface of the third device;
a first molding part surrounding the first device and the second device on the first substrate;
a second molding part surrounding the third device on the first molding part;
first through-electrodes vertically penetrating the first molding part between the first device and the second device to electrically connect the first substrate to the third device;
second through-electrodes vertically penetrating the first molding part; and
third through-electrodes vertically penetrating the second molding part to be electrically connected to the second through-electrodes,
wherein the third device vertically overlaps the whole of the first device and the whole of the second device,
wherein the first device is connected to the first substrate through solder bumps at a bottom surface of the first device, and
wherein the second device is connected to the first substrate through an adhesive film on a bottom surface of the second device.

13. The semiconductor package of claim 12 , further comprising:
a redistribution layer disposed between the first molding part and the second molding part,
wherein the third device is mounted on a top surface of the redistribution layer by using connection terminals, and
wherein each of the first device and the second device have bumps exposed at a top surface of the first molding part, and the first device and the second device are mounted on a bottom surface of the redistribution layer by using the bumps.

14. The semiconductor package of claim 12 , further comprising:
an intermediate layer provided between the first molding part and the second molding part; and
pads provided in the intermediate layer,
wherein the first device and the second device are electrically connected to the pads on a bottom surface of the intermediate layer, and the third device is electrically connected to the pads on a top surface of the intermediate layer.

15. The semiconductor package of claim 12 , wherein a width of the first device and a width of the second device are less than a width of the third device.

16. The semiconductor package of claim 12 , wherein the first device comprises:
a base layer;
a circuit layer provided on the base layer and provided at the first active surface of the first device;
bumps provided on the circuit layer and electrically connected to the circuit layer; and
vias vertical

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Doohwan
• Choi Wonkyoung
• Lee Jeongho

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title