Fan-out 3D IC integration structure without substrate and method of making the same

Patent metadata

Field	Value
Publication number	US-9837378-B2
Application number	US-201514954679-A
Country	US
Kind code	B2
Filing date	Nov 30, 2015
Priority date	Oct 23, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A three-dimensional (3D) integrated circuit (IC) package is disclosed that contains a plurality of encapsulated layers stacked upon each other without the use of a substrate(s). Each of the encapsulated layers contains an encapsulating material, a die, an interconnecting interface, and vertical vias. The encapsulating material forms the surfaces of an encapsulated layer and encapsulates the die. The interconnecting interface provides an interface at a surface of the encapsulated layer for the die to electrically connect to other dies or external components. The vertical vias provide a conduction path between interconnecting interfaces of different encapsulated layers.

First claim

What is claimed is:

1. An integrated circuit (IC) package, comprising:
a first encapsulated layer, including:
a first encapsulating material to form opposing first and second surfaces of the first encapsulated layer;
one or more first dies encapsulated by the first encapsulating material; and
a first interconnect layer to provide an electrical interface for the one or more first dies, the first interconnect layer disposed within the first encapsulating material and connected to the first surface of the first encapsulating layer; and

a second encapsulated layer, including:
a second encapsulating material to form opposing first and second surfaces of the second encapsulated layer, the first surface of the second encapsulated layer disposed directly on the second surface of the first encapsulated layer;
one or more second dies encapsulated by the second encapsulating material; and
a second interconnect layer to provide an electrical interface for the one or more second dies, the second interconnect layer disposed within the second encapsulating material and exposed to and contacting the second surface of the first encapsulated layer.

2. The IC package of claim 1 , wherein the first encapsulated layer further comprises first vertical vias configured to provide an electrical path between the first interconnect layer and the second interconnect layer.

3. The IC package of claim 2 , wherein the first interconnect layer comprises input/output (I/O) pads, first die contact pads, and traces configured to connect the I/O pads to the first die contact pads.

4. The IC package of claim 3 , wherein the first vertical vias are configured to contact the I/O pads and via pads on the second interconnect layer.

5. The IC package of claim 3 , wherein the first encapsulated layer further comprises first die connections configured to connect an active surface of the one or more first dies to the first die contact pads.

6. The IC package of claim 3 , further comprising solder balls configured to electrically connect the I/O pads to a printed circuit board (PCB).

7. The IC package of claim 2 , wherein the second encapsulated layer further comprises second vertical vias configured to provide an electrical path between the second interconnect layer and a component external to the IC package.

8. The IC package of claim 7 , wherein the second interconnect layer comprises via pads, second die contact pads, and traces configured to connect the via pads to the second die contact pads.

9. The IC package of claim 8 , wherein the second vertical vias are configured to contact the via pads and are exposed at the second interconnect layer.

10. The IC package of claim 9 , further comprising an external interconnect layer to provide an electrical interface between the IC package and the component external to the IC package, wherein the external interconnect layer is disposed on the second surface of the second encapsulated layer.

11. The IC package of claim 8 , wherein the second interconnect layer further comprises second die connections configured to connect the one or more second dies to the second die contact pads.

12. The IC package of claim 1 , further comprising one or more additional encapsulated layers, wherein each of the one or more additional encapsulated layers comprises:
an encapsulating material to form opposing first and second surfaces of the one or more additional encapsulated layers, the first surface of the one or more additional encapsulated layers disposed on a predetermined surface of a preceding encapsulated layer;
one or more dies encapsulated by the encapsulating material; and
an interconnect layer to provide an electrical interface for the one or more dies, the interconnect layer disposed within the encapsulating material and exposed to and contacting the predetermined surface of the preceding encapsulated layer.

Assignees

• Avago Technologies General Ip

Inventors

• Khan Rezaur Rahman
• Zhao Sam Ziqun

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W72/07141

  Means for applying energy, e.g. ovens or lasers · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title