Semiconductor package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11942446-B2
Application number	US-202117165429-A
Country	US
Kind code	B2
Filing date	Feb 2, 2021
Priority date	Jun 22, 2020
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

A semiconductor package includes at least one second semiconductor chip stacked on a first semiconductor chip. An underfill layer is interposed between the first semiconductor chip and the at least one second semiconductor chip. The first semiconductor chip includes a first substrate, a first passivation layer disposed on the first substrate. The first passivation layer includes a first recess region. A first pad covers a bottom surface and sidewalls of the first recess region. The at least one second semiconductor chip includes a second substrate, a second passivation layer disposed adjacent to the first substrate, a conductive bump protruding outside the second passivation layer towards the first semiconductor chip and an inter-metal compound pattern disposed in direct contact with both the conductive bump and the first pad. The underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern.

First claim

What is claimed is:

1. A semiconductor package comprising:
at least one second semiconductor chip stacked on a first semiconductor chip; and
an underfill layer interposed between the first semiconductor chip and the at least one second semiconductor chip, the underfill layer is composed of an insulating resin and fillers;
wherein the first semiconductor chip comprises: a first substrate; a first passivation layer disposed on the first substrate, the first passivation layer including a first recess region extending from an uppermost surface of the first passivation layer to a lowermost surface of the first passivation layer; and a first pad covering a bottom surface and sidewalls of the first recess region,
wherein the at least one second semiconductor chip comprises: a second substrate; a second passivation layer disposed adjacent to the first substrate; a conductive bump protruding outside the second passivation layer towards the first semiconductor chip; and an inter-metal compound pattern disposed in the first recess region and positioned between sidewalls of the first pad, a lowermost surface of the inter-metal compound pattern is in direct contact with the first pad in the first recess region and an uppermost surface of the inter-metal compound pattern is in direct contact with the conductive bump,
wherein the underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern and extends within the first recess region, a lowermost surface of the underfill layer tending within the first recess region is positioned below the uppermost surface of the first passivation layer,
wherein the lowermost surface of the inter-metal compound pattern has a maximum width that is greater than a maximum width of the uppermost surface of the inter-metal compound pattern.

2. The semiconductor package of claim 1 , wherein the inter-metal compound pattern protrudes from a top surface of the first pad.

3. The semiconductor package of claim 1 , wherein a top surface of the inter-metal compound pattern includes a concave region disposed adjacent to the conductive bump.

4. The semiconductor package of claim 1 , wherein a portion of the underfill layer is interposed between at least one inner sidewall of the first pad and at least one sidewall of the inter-metal compound pattern within the first recess region.

5. The semiconductor package of claim 1 , wherein the first semiconductor chip further comprises: a first through-electrode penetrating the first substrate and directly contacting the first pad.

6. The semiconductor package of claim 1 , wherein the first semiconductor chip further comprises: at least one redistribution insulating layer interposed between the first substrate and the first passivation layer; and at least one redistribution pattern disposed in direct contact with the at least one redistribution insulating layer, respectively,
wherein the first pad is in direct contact with the at least one redistribution pattern.

7. The semiconductor package of claim 1 , wherein:
the first pad and the conductive bump include a first metal; and
the inter-metal compound pattern includes an alloy of the first metal and a second metal; and
a melting point of the second metal is lower than a melting point of the first metal.

8. The semiconductor package of claim 1 , further comprising:
the at least one second semiconductor chip comprises a plurality of second semiconductor chips;
a mold layer covering the first semiconductor chip and the at least one second semiconductor chip,
wherein the at least one second semiconductor chip further comprises: a third passivation layer disposed on a top surface of the second substrate, the third passivation layer including a second recess region; and a second pad covering inner sidewalls and a bottom surface of the second recess region and having a concave upper region,
wherein the mold layer fills the concave upper region.

9. The semiconductor package of claim 8 , wherein the at least one second semiconductor chip further comprises:
a conductive bonding layer disposed on the second pad,
wherein the second pad includes a first metal, and the conductive bonding layer includes a second metal,
wherein a melting point of the second metal is lower than a melting point of the first metal.

10. A semiconductor package comprising:
at least one semiconductor chip stacked on a package substrate; and
an underfill layer interposed between the package substrate and the at least one semiconductor chip, the underfill layer is composed of an insulating resin and fillers;
wherein the package substrate comprises: a first passivation layer including a first recess region extending from an uppermost surface of the first passivation layer to a lowermost surface of the first passivation layer; and a first pad covering a bottom surface and sidewalls of the first recess region, the first pad having a concave top surface,
wherein the at least one semiconductor chip comprises: a conductive bump protruding toward the package substrate; and an inter-metal compound pattern disposed in the first recess region and positioned between sidewalls of the first pad, the inter-metal compound pattern is in direct contact with both the conductive bump and the first pad,
wherein the underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern and extends within the first recess region, a lowermost surface of the underfill layer extending within the first recess region is positioned below the uppermost surface of the first passivation layer.

11. The semiconductor package of claim 10 , wherein the inter-metal compound pattern protrudes from a top surface of the first pad.

12. The semiconductor package of claim 10 , wherein a top surface of the inter-metal compound pattern includes a concave region disposed adjacent to the conductive bump.

13. The semiconductor package of claim 10 , wherein a portion of the underfill layer is interposed between at least one inner sidewall of the first pad and at least one sidewall of the inter-metal compound pattern.

14. A semiconductor package comprising:
at least one second semiconductor chip stacked on a first semiconductor chip; and
an underfill layer interposed between the first semiconductor chip and the at least one second semiconductor chip, the underfill layer is composed of an insulating resin and fillers;
wherein the first semiconductor chip comprises: a first substrate; a first through-electrode penetrating the first substrate; a first passivation layer disposed on the first substrate and including a first recess region exposing the first through-electrode, the first recess region extending from an uppermost surface of the first passivation layer to a lowermost surface of the first passivation laver; and a first pad covering a bottom surface and sidewalls of the first recess region, the first pad is in direct contact with the first through-electrode, wherein the at least one second semiconductor chip comprises: a second substrate; a second passivation layer adjacent to the first substrate; a conductive bump protruding outside the second passivation layer toward the first semiconductor chip; and an inter-metal compound pattern disposed in the first recess region and positioned between sidewalls of the first pad, the inter-metal compound has an uppermost surface in direct contact with a lowermost surface of the conductive bump and a lowermost surface in direct contact with the first pad,
wherein the underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern and extends within th

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyoeun
• Seo Sunkyoung
• Yeon Seunghoon
• Jo Chajea

Classifications

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W74/131

  the semiconductor body being only partially enclosed · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title