Copper structures with intermetallic coating for integrated circuit chips

Patent metadata

Field	Value
Publication number	US-10461052-B2
Application number	US-201715663331-A
Country	US
Kind code	B2
Filing date	Jul 28, 2017
Priority date	May 26, 2015
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

An integrated circuit (IC) chip includes a copper structure with an intermetallic coating on the surface. The IC chip includes a substrate with an integrated circuit. A metal pad electrically connects to the integrated circuit. The copper structure electrically connects to the metal pad. A solder bump is disposed on the copper structure. The surface of the copper structure has a coating of intermetallic. The copper structure can be a redistribution layer and a copper pillar that is disposed on the redistribution layer.

First claim

What is claimed is:

1. An integrated circuit (IC) chip comprising:
a substrate comprising an integrated circuit;
a metal pad disposed on the substrate and electrically connects to the integrated circuit;
a redistribution layer that electrically connects to the metal pad;
a copper pillar that is disposed on and electrically connects to the redistribution layer;
a solder bump that is disposed on and electrically connects to the copper pillar; and
a tin-copper intermetallic coating that is formed on a surface of the copper pillar and the redistribution layer.

2. The IC chip of claim 1 , wherein the metal pad comprises an input/output pad of the IC chip.

3. The IC chip of claim 1 , wherein the solder bump comprises tin.

4. The IC chip of claim 1 , wherein the metal pad comprises aluminum.

5. The IC chip of claim 1 , further comprising a copper seed layer disposed between the metal pad and the redistribution layer.

6. The IC chip of claim 5 , wherein the copper seed layer comprises a titanium-copper stack.

7. The IC chip of claim 5 , wherein the tin-copper intermetallic is formed on a surface of the copper seed layer.

8. An integrated circuit (IC) chip comprising:
a substrate comprising an integrated circuit;
a first copper structure comprising a first copper pillar formed on a first metal pad that electrically connects to the integrated circuit, a first solder bump formed on the first copper pillar, a first redistribution layer between the first copper pillar and the first metal pad, and a first intermetallic coating on a surface of the first redistribution layer and on a surface of the first copper pillar that faces toward a surface of a second copper pillar of a second copper structure; and
the second copper structure that is adjacent to the first copper structure, the second copper structure comprising the second copper pillar formed on a second metal pad that electrically connects to the integrated circuit, a second solder bump formed on the second copper pillar, a second redistribution layer between the second copper pillar and the second metal pad, and a second intermetallic coating on a surface of the second distribution layer and on the surface of the second copper pillar that faces toward the surface of the first copper pillar.

9. The IC chip of claim 8 , further comprising:
a passivation layer between the first metal pad and the first copper pillar and between the second metal pad and the second copper pillar.

10. The IC chip of claim 9 , wherein the passivation layer comprises a first plurality of vias through which the first copper pillar electrically connects to the first metal pad and a second plurality of vias through which the second copper pillar electrically connects to the second metal pad.

11. The IC chip of claim 8 , wherein the first intermetallic coating and the second intermetallic coating each comprises a tin-copper intermetallic.

12. An integrated circuit (IC) chip comprising:
a first metal pad that is adjacent to a second metal pad;
a first copper structure comprising a first redistribution layer on the first metal pad, a first copper pillar on the first redistribution layer, and a first tin-copper intermetallic coating on a surface of the first redistribution layer and on a surface of the first copper pillar;
a second copper structure comprising a second redistribution layer on the second metal pad, a second copper pillar on the second redistribution layer, and a second tin-copper intermetallic coating on a surface of the second redistribution layer and on a surface of the second copper pillar; and
a first solder bump on the first copper pillar; and
a second solder bump on the second copper pillar.

13. The IC chip of claim 12 , further comprising:
a passivation layer between the first metal pad and the first copper pillar and between the second metal pad and the second copper pillar.

14. The IC chip of claim 13 , wherein the passivation layer comprises a first plurality of vias through which the first copper pillar electrically connects to the first metal pad and a second plurality of vias through which the second copper pillar electrically connects to the second metal pad.

Assignees

• Monolithic Power Systems Inc

Inventors

• Jiang Hunt Hang

Classifications

• H10W72/60

  Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9232

  with additional elements interposed between layers · CPC title