Method for self-aligned solder reflow bonding and devices obtained thereof

Patent metadata

Field	Value
Publication number	US-9978710-B2
Application number	US-201615385653-A
Country	US
Kind code	B2
Filing date	Dec 20, 2016
Priority date	Dec 24, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

First claim

What is claimed is:

1. A method for producing a stack of semiconductor devices, the method comprising:
providing a first semiconductor device, the first semiconductor device comprising: a dielectric layer with an exposed upper surface, a hole through the dielectric layer, a sidewall and a bottom of the hole lined with a metal layer, a solder material on the metal layer partially filling the metal lined hole from the bottom upward thereby forming a solder hole;
providing a second semiconductor device, the second semiconductor device comprising: a compliant layer with an exposed main surface, a metal protrusion through the compliant layer and the metal protrusion further extending perpendicular from the exposed main surface, a capping layer covering the metal protrusion and separating the metal protrusion from the compliant layer;
mounting the second semiconductor device on the first semiconductor device by landing the metal protrusion in the solder hole, and contacting the solder material with the capping layer, wherein after mounting, the exposed main surface of the compliant layer is spaced from the exposed upper surface of the dielectric layer; and
after mounting the second semiconductor device on the first semiconductor device, reflowing the solder material, thereby filling the hole with reflowed material, wherein after reflowing the first semiconductor device and the second semiconductor device are bonded and the main surface of the compliant layer is contacting the upper surface of the dielectric layer.

2. The method according to claim 1 , wherein the capping layer comprises a wetting material for the solder material.

3. The method according to claim 1 , wherein the metal layer is a seed layer for plating of the solder material.

4. The method according to claim 1 , wherein the metal lined hole has continuously sloped sidewalls and a circumference of the metal lined hole continuously decreases closer to the bottom of the hole.

5. The method according to claim 1 , wherein the reflowed material comprises inter-metal-compounds (IMCs) formed from any of: the solder material and the capping layer, the solder material and the metal layer, and the solder material and the metal protrusion.

6. The method according to claim 1 , wherein providing the first semiconductor device comprises:
providing the hole in the dielectric layer;
providing the metal layer on the dielectric layer;
plating the solder material on the metal layer, using the metal layer as a seed layer; and
performing chemical mechanical polishing (CMP), thereby removing the solder material and dielectric layer to expose the upper surface of the dielectric layer, and leaving the metal lined hole sidewalls covered with solder material and the metal lined hole partially filled with solder material.

7. A method according to claim 1 , wherein the bottom of the hole through the dielectric layer exposes a contact pad of the first semiconductor device, and the wherein the metal protrusion is part of a Through Substrate Via of the second semiconductor device.

8. A stack of semiconductor devices comprising:
a first semiconductor device comprising a dielectric layer with an upper surface, and a hole through the dielectric layer, a sidewall and a bottom of the hole lined with a non-consumed metal layer; and
a second semiconductor device comprising a compliant layer with a main surface, a metal protrusion through the compliant layer, and a capping layer separating the metal protrusion from the compliant layer, wherein the main surface of the compliant layer contacts the upper surface of the dielectric layer, wherein the hole is filled and comprises a reflowed material, the reflowed material bonded to the metal protrusion and to the non-consumed metal layer, the reflowed material comprising a solder material.

9. The stack of semiconductor devices according to claim 8 , wherein the reflowed material further comprises inter-metal-compounds (IMCs) formed from any of: the solder material and the material of the capping layer, the solder material and the material of the non-consumed metal layer, and the solder material and the material of the metal protrusion.

10. The stack of semiconductor devices according to claim 8 , wherein the hole has a continuously sloped sidewall and a circumference of the hole continuously decreases closer to the bottom of the hole.

Assignees

• Imec Vzw
• Univ Leuven Kath

Inventors

• Dubey Vikas
• Beyne Eric
• Derakhshandeh Jaber

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W74/47

  comprising organic materials, e.g. plastics or resins · CPC title