Thin semiconductor package for notched semiconductor die

Patent metadata

Field	Value
Publication number	US-11942369-B2
Application number	US-202016942916-A
Country	US
Kind code	B2
Filing date	Jul 30, 2020
Priority date	Aug 17, 2017
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

First claim

What is claimed is:

1. A semiconductor package comprising:
a die comprising a notch located around a perimeter of a sixth side of the die, the die comprising a first side opposing the sixth side, the first side of the die comprising a plurality of electrical contacts;
a second molding compound coupled over the sixth side of the die and into the notch;
a first molding compound coupled over the first side of the die, the first molding compound forming a thickness above the first side; and
a metal layer coupled to the sixth side of the die;
wherein a thickness of the plurality of electrical contacts is substantially the same as the thickness of the first molding compound;
wherein an entirety of the second molding compound is coupled between the metal layer and the die;
wherein each of the metal layer, the second molding compound, and the die all extend to an outermost side surface of the semiconductor package.

2. The package of claim 1 , wherein the second molding compound contacts the metal layer.

3. The package of claim 1 , wherein the first molding compound and second molding compound are entirely separated by the die.

4. The package of claim 1 , wherein the metal layer extends to an outermost sidewall of the semiconductor package.

5. A semiconductor package comprising:
a die comprising a notch located around a perimeter of a sixth side of the die, the die comprising a first side opposing the sixth side, the first side of the die comprising a plurality of electrical contacts;
a second molding compound coupled into the notch;
a first molding compound coupled over the first side of the die, the first molding compound forming a thickness above the first side; and
a metal layer coupled to the sixth side of the die, coupled directly over the second molding compound, and extending to an outermost side surface of the semiconductor package;
wherein a thickness of the plurality of electrical contacts is substantially the same as the thickness of the first molding compound;
wherein the die is exposed on four sidewalls of the semiconductor package; and
wherein an outermost edge of the first molding compound extends to a perimeter of the first side of the die.

6. The package of claim 5 , wherein a portion of a second side, a portion of a third side, a portion of a fourth side, and a portion of a fifth side of the die are exposed at an outer surface of the semiconductor package between the first molding compound and the second molding compound.

7. The package of claim 5 , wherein a portion of a second side, a portion of a third side, a portion of a fourth side, and a portion of a fifth side of the die are exposed on an outer surface of the semiconductor package.

8. The package of claim 5 , wherein, of the first molding compound and second molding compound, only the second molding compound contacts the metal layer.

9. The package of claim 5 , wherein the first molding compound and second molding compound are separated by a second side, a third side, a fourth side, and a fifth side of the die.

10. The package of claim 5 , wherein the first molding compound is entirely separated from the second molding compound by the die.

11. The semiconductor package of claim 5 , wherein an entirety of the second molding compound is within the notch and between the die and the metal layer.

12. A semiconductor package comprising:
a die comprising a notch located around a perimeter of a sixth side of the die, the die comprising a first side opposing the sixth side, the first side of the die comprising a plurality of electrical contacts;
an entirety of a second molding compound coupled within the notch;
a first molding compound coupled over the first side of the die; and
a metal layer coupled to the sixth side of the die, coupled directly over the second molding compound, and extending to an outermost sidewall of the semiconductor package;
wherein an outermost edge of the metal layer, an outermost edge of the second molding compound, an outermost edge of the die, an outermost edge of the first molding compound, and an outermost sidewall of the semiconductor package all lie within a same plane.

13. The semiconductor package of claim 12 , wherein an outer perimeter of the metal layer is the same as an outer perimeter of the semiconductor package.

14. The semiconductor package of claim 12 , wherein the die is exposed on four sidewalls of the semiconductor package.

15. The semiconductor package of claim 12 , wherein the second molding compound is the only molding compound that contacts the metal layer.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Krishnan Shutesh
• Wang Sw Wei
• Chew Ch
• Liew How Kiat
• Tan Fui Fui

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title