Device including semiconductor chips and method for producing such device

Patent metadata

Field	Value
Publication number	US-10903180-B2
Application number	US-201815949632-A
Country	US
Kind code	B2
Filing date	Apr 10, 2018
Priority date	Oct 31, 2013
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

First claim

What is claimed is:

1. A device, comprising:
a first semiconductor chip comprising a first face and a second face, the second face on an opposite side of the first semiconductor chip than the first face of the first semiconductor chip, wherein a first contact pad of the first semiconductor chip is arranged over the first face of the first semiconductor chip;
a second semiconductor chip comprising a first face and a second face, the second face on an opposite side of the second semiconductor chip than the first face of the second semiconductor chip, wherein a first contact pad of the second semiconductor chip is arranged over the first face of the second semiconductor chip; and
a third semiconductor chip comprising a first face and a second face, the second face on an opposite side of the third semiconductor chip than the first face of the third semiconductor chip, wherein a first contact pad of the third semiconductor chip is arranged over the first face of the third semiconductor chip,
wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction, and where the first face of the third semiconductor chip faces in the first direction or the second direction,
wherein the first semiconductor chip is located laterally outside of an outline of the second semiconductor chip and laterally outside of an outline of the third semiconductor chip, wherein the third semiconductor chip is located laterally outside of the outline of the second semiconductor chip, wherein the third semiconductor chip has a third thickness that is different from a first thickness of the first semiconductor chip and different from a second thickness of the second semiconductor chip, and wherein the first semiconductor chip, the second semiconductor chip and the third semiconductor chip are at least partly embedded in a same material layer,
wherein the first face of the first semiconductor chip is positioned at a height relative to a major surface of the device which is between a first height relative to the major surface of the device of the first face of the third semiconductor chip and the height relative to the major surface of the device of the second face of the third semiconductor chip, wherein the first face of the second semiconductor chip is positioned at a second height relative to the major surface of the device which is between the first height of the first face of the third semiconductor chip and the height of the second face of the third semiconductor chip, and wherein the first face of the second semiconductor chip is positioned at the second height which is between the height relative to the major surface of the second face of the first semiconductor chip and the height of the first face of the first semiconductor chip.

2. The device of claim 1 , wherein the second face of the second semiconductor chip is positioned at the height relative to the major surface of the device which is between the height of the first face of the first semiconductor chip and the height of the second face of the third semiconductor chip.

3. The device of claim 1 , wherein at least one of the first semiconductor chip and the second semiconductor chip comprises a power semiconductor.

4. The device of claim 1 , wherein the first semiconductor chip comprises a second contact pad arranged over the second face of the first semiconductor chip.

5. The device of claim 1 , wherein the material layer comprises at least one of a laminate, an epoxy, a filled epoxy, glass fiber filled epoxy, an imide, a thermoplast and a duroplast polymer or polymer blends.

6. The device of claim 4 , further comprising:
a patterned electrically conductive layer arranged over the second face of the first semiconductor chip and electrically coupled to the second contact pad of the first semiconductor chip by one of a plated connection and a microvia array or through one or multiple openings over a third contact pad.

7. The device of claim 6 , wherein the patterned electrically conductive layer is arranged over the first face of the second semiconductor chip and electrically coupled to the first contact pad of the second semiconductor chip by a via connection.

8. A device, comprising:
a first semiconductor chip comprising a first face and a second face, the second face on an opposite side of the first semiconductor chip than the first face of the first semiconductor chip, wherein a first contact pad of the first semiconductor chip is arranged over the first face of the first semiconductor chip;
a second semiconductor chip comprising a first face and a second face, the second face on an opposite side of the second semiconductor chip than the first face of the second semiconductor chip, wherein a first contact pad of the second semiconductor chip is arranged over the first face of the second semiconductor chip; and
a third semiconductor chip comprising a first face and a second face, the second face on an opposite side of the third semiconductor chip than the first face of the third semiconductor chip, wherein a first contact pad of the third semiconductor chip is arranged over the first face of the third semiconductor chip,
wherein the first semiconductor chip is located laterally outside of an outline of the second semiconductor chip and laterally outside of an outline of the third semiconductor chip, wherein the third semiconductor chip is located laterally outside of the outline of the second semiconductor chip,
wherein the third semiconductor chip has a third thickness that is different from a first thickness of the first semiconductor chip and different from a second thickness of the second semiconductor chip,
wherein the first semiconductor chip, the second semiconductor chip and the third semiconductor chip are at least partly embedded in a same material layer,
wherein the first face of the first semiconductor chip is positioned at a height relative to a major surface of the device which is between a first height relative to the major surface of the device of the first face of the third semiconductor chip and the height relative to the major surface of the device of the second face of the third semiconductor chip, wherein the first face of the second semiconductor chip is positioned at a second height relative to the major surface of the device which is between the first height of the first face of the third semiconductor chip and the height of the second face of the third semiconductor chip, and wherein the first face of the second semiconductor chip is positioned at the second height which is between the height relative to the major surface of the second face of the first semiconductor chip and the height of the first face of the first semiconductor chip.

9. The device of claim 8 , wherein the second face of the second semiconductor chip is positioned at the height relative to the major surface of the device which is between the height of the first face of the first semiconductor chip and the height of the second face of the third semiconductor chip.

10. The device of claim 8 , further comprising:
a patterned electrically conductive layer arranged over the second face of the first semiconductor chip opposite to the first face of the first semiconductor chip and electrically coupled to a second contact pad of the first semiconductor chip by one of a plated connection and a microvia array or through one or multiple openings over the second contact pad,
wherein the patterned electrically conductive layer is arranged over the first face of the second semiconductor chip and

Assignees

• Infineon Technologies Ag

Inventors

• Palm Petteri
• Scharf Thorsten

Classifications

• H10W80/011

  Manufacture or treatment of pads or other interconnections to be direct bonded · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/07323

  Active alignment, e.g. using optical alignment using marks or sensors · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title