Semiconductor package with via-coupled power transistors

Patent metadata

Field	Value
Publication number	US-9496168-B2
Application number	US-201514605675-A
Country	US
Kind code	B2
Filing date	Jan 26, 2015
Priority date	Mar 18, 2014
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

In one implementation, a semiconductor package includes a carrier including first and second conductive segments, and first and second transistors attached respectively to the first and second conductive segments. The semiconductor package also includes a dielectric material formed in exposed portions of the first and second conductive segments, a first via extending through the dielectric material to the first conductive segment, and a second via extending through the dielectric material to the second conductive segment. A solder material fills each of the vias, the solder material protruding beyond the dielectric material and configured to electrically, thermally, and mechanically connect the carrier to a mounting surface for the semiconductor package.

First claim

The invention claimed is:

1. A semiconductor package comprising:
a carrier including first and second conductive segments;
first and second transistors attached respectively to said first and second conductive segments;
a dielectric material formed in exposed portions of said first and second conductive segments;
a first via extending through said dielectric material to said first conductive segment, and a second via extending through said dielectric material to said second conductive segment;
a solder material filling each of said first and second vias, said solder material protruding beyond said dielectric material and configured to electrically, thermally, and mechanically connect said carrier to a mounting surface for said semiconductor package.

2. The semiconductor package of claim 1 , wherein said vias comprise laser vias.

3. The semiconductor package of claim 1 , wherein said carrier is configured as an integrated heat spreader of said semiconductor package.

4. The semiconductor package of claim 1 , wherein said first and second transistors comprise power transistors implemented in a power switching stage of a voltage converter.

5. The semiconductor package of claim 4 , wherein said semiconductor package is configured to utilize said mounting surface to provide a switch node of said power switching stage.

6. The semiconductor package of claim 1 , wherein said carrier comprises at least a portion of a lead frame.

7. The semiconductor package of claim 1 , wherein said first and second transistors comprise vertical power field-effect transistors (FETs).

8. The semiconductor package of claim 1 , wherein said first and second transistors comprise silicon FETs.

9. The semiconductor package of claim 1 , wherein said first and second transistors comprise HI-Nitride high electron mobility transistors (HEMTs).

10. The semiconductor package of claim 1 , further comprising a driver integrated circuit (IC) attached to a third conductive segment of said carrier, said driver IC configured to drive at least one of said first and second transistors.

11. A method for fabricating a semiconductor package, said method comprising:
attaching first and second transistors to respective first and second conductive segments of a carrier;
forming a dielectric material in exposed portions of said carrier;
forming a first via extending through said dielectric material to said first conductive segment, and a second via extending through said dielectric material to said second conductive segment;
filling said vias with a solder material, said solder material protruding beyond said dielectric material and configured to electrically, thermally, and mechanically connect said carrier to a mounting surface for said semiconductor package.

12. The method of claim 11 , wherein forming said vias comprises utilizing a laser drill to form first and second laser vias.

13. The method of claim 11 , wherein said carrier is configured as an integrated heat spreader of said semiconductor package.

14. The method of claim 11 , wherein said first and second transistors comprise power transistors implemented in a power switching stage of a voltage converter.

15. The method of claim 14 , wherein said semiconductor package is configured to utilize said mounting surface to provide a switch node of said power switching stage.

16. The method of claim 11 , wherein said carrier comprises at least a portion of a lead frame.

17. The method of claim 11 , wherein said first and second transistors comprise vertical power field-effect transistors (FETs).

18. The method of claim 11 , wherein said first and second transistors comprise silicon FETs.

19. The method of claim 11 , wherein said first and second transistors comprise III-Nitride high electron mobility transistors (HEMTs).

20. The method of claim 11 , further comprising attaching a driver integrated circuit (IC) to a third conductive segment of said carrier, said driver IC being configured to drive at least one of said first and second transistors.

Assignees

• Infineon Technologies Americas Corp

Inventors

• Cho Eung San

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/07336

  Soldering or alloying · CPC title

• H10W72/07331

  Connecting techniques · CPC title