Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication

Patent metadata

Field	Value
Publication number	US-11929320-B2
Application number	US-202217709032-A
Country	US
Kind code	B2
Filing date	Mar 30, 2022
Priority date	Dec 27, 2019
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

First claim

What is claimed is:

1. A device, comprising:
a metallization structure coupled to a semiconductor device; and
a transistor above the metallization structure, the transistor comprising:
a body comprising a semiconductor material;
a source structure on a first portion of the body and a drain structure on a second portion of the body; and
a gate structure comprising a first portion in a recess in the body and a second portion between the source structure and the drain structure;
a first contact coupled with the source structure or the drain structure, wherein the first contact is in contact with the metallization structure; and
a dielectric spacer on and in contact with a portion of the body between the gate structure and the source structure or the drain structure.

2. The device of claim 1 , wherein the first portion of the gate structure in the recess comprises not more than half of a thickness of the body.

3. The device of claim 2 , wherein the thickness of the body is not less than 10 nm, and wherein the first portion of the gate structure has a lateral dimension orthogonal to the thickness of not less than 30 nm.

4. The device of claim 1 , wherein the first portion of the gate structure extends laterally under a portion of the source structure or the drain structure.

5. The device of claim 1 , further comprising a dielectric spacer on a portion of the source structure or the drain structure, wherein the second portion of the gate structure is directly adjacent to the source structure or the drain structure, and wherein the gate structure further comprises a third portion on the second portion, wherein the third portion is directly adjacent to the dielectric spacer.

6. The device of claim 1 , wherein the source structure and the drain structure each comprise a first region directly adjacent to the body, wherein the first regions comprise no dopants and a second regions above the first regions comprise a dopant.

7. The device of claim 1 , wherein the first contact is in contact with a sidewall of the body and an uppermost surface of the metallization structure.

8. The device of claim 1 , further comprising:
a processor; and
a transceiver coupled to the processor, wherein the transceiver or the processor comprises the metallization structure, the semiconductor device, and the transistor.

9. A device, comprising:
a metallization structure coupled to a semiconductor device; and
a transistor above the metallization structure, the transistor comprising:
a body comprising a semiconductor material;
a source structure on a first portion of the body and a drain structure on a second portion of the body; and
a gate structure comprising a first portion in a recess in the body and a second portion between the source structure and the drain structure; and
a first contact coupled with the source structure or the drain structure, wherein the first contact is in contact with the metallization structure, wherein the first contact is in contact with a sidewall of the body and an uppermost surface of the metallization structure.

10. The device of claim 9 , wherein the first portion of the gate structure in the recess comprises not more than half of a thickness of the body.

11. The device of claim 10 , wherein the thickness of the body is not less than 10 nm, and wherein the first portion of the gate structure has a lateral dimension orthogonal to the thickness of not less than 30 nm.

12. The device of claim 9 , wherein the first portion of the gate structure extends laterally under a portion of the source structure or the drain structure.

13. The device of claim 9 , further comprising a dielectric spacer on a portion of the source structure or the drain structure, wherein the second portion of the gate structure is directly adjacent to the source structure or the drain structure, and wherein the gate structure further comprises a third portion on the second portion, wherein the third portion is directly adjacent to the dielectric spacer.

14. The device of claim 9 , wherein the source structure and the drain structure each comprise a first region directly adjacent to the body, wherein the first regions comprise no dopants and a second regions above the first regions comprise a dopant.

15. The device of claim 9 , further comprising:
a processor; and
a transceiver coupled to the processor, wherein the transceiver or the processor comprises the metallization structure, the semiconductor device, and the transistor.

16. A device, comprising:
a metallization structure coupled to a semiconductor device below the metallization structure; and
a transistor above the metallization structure, the transistor comprising:
a body comprising a single crystal group III-V or group IV semiconductor material;
a source structure on a first portion of the body and a drain structure on a second portion of the body; and
a gate structure comprising a first portion in a recess in the body and a second portion between the source structure and the drain structure, wherein the first portion of the gate structure extends laterally under a portion of the source structure or the drain structure; and
a first contact coupled with the source structure or the drain structure, wherein the first contact is coupled to the metallization structure.

17. The device of claim 16 , wherein the first portion of the gate structure in the recess comprises not more than half of a thickness of the body, wherein the thickness of the body is not less than 10 nm, and wherein the first portion of the gate structure has a lateral dimension orthogonal to the thickness of not less than 30 nm.

18. The device of claim 16 , further comprising a dielectric spacer on a portion of the source structure or the drain structure, wherein the second portion of the gate structure is directly adjacent to the source structure or the drain structure, and wherein the gate structure further comprises a third portion on the second portion, wherein the third portion is directly adjacent to the dielectric spacer.

19. The device of claim 16 , further comprising:
a processor; and
a transceiver coupled to the processor, wherein the transceiver or the processor comprises the metallization structure, the semiconductor device, and the transistor.

Assignees

• Intel Corp

Inventors

• Dewey Gilbert
• Keech Ryan
• Bomberger Cory
• Huang Cheng-Ying
• Agrawal Ashish
• Rachmady Willy
• Murthy Anand

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914

  using bonding · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title