Interlayer via

Patent metadata

Field	Value
Publication number	US-9711501-B1
Application number	US-201615276333-A
Country	US
Kind code	B1
Filing date	Sep 26, 2016
Priority date	Sep 26, 2016
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A semiconductor device is provided. The semiconductor device includes a lower layer, an upper layer and an interlayer via. The lower layer includes a lower substrate, lower electronic devices, metallization elements and contact elements. One of the lower electronic devices includes a field effect transistor (FET), lower contacts and spacers interposed between the FET and the lower contacts. At least one of the contact elements is electrically coupled between a metallization element and one of the lower contacts to form a stack. The upper layer includes an upper substrate and upper electronic devices. One of the upper electronic devices includes an FET, upper contacts and spacers interposed between the FET and the upper contacts. The upper substrate and one of the upper contacts define a through-hole aligned with the stack. The interlayer via extends through the through-hole to electrically couple the stack and the one of the upper contacts.

First claim

What is claimed is:

1. An integrated circuit comprising:
a lower layer comprising a lower substrate, lower electronic devices, metallization elements and contact elements;
wherein one of the lower electronic devices comprises:
a field effect transistor (FET) comprising a gate,
lower contacts comprising complementary source or drain epitaxial contacts, and
spacers interposed between the gate of the FET and the lower contacts;

wherein at least one of the contact elements is communicatively coupled between a metallization element and one of the lower contacts to form a stack;
an upper layer comprising an upper substrate and upper electronic devices;
wherein one of the upper electronic devices comprises:
an FET comprising a gate,
upper contacts comprising complementary source or drain epitaxial contacts, and
spacers interposed between the gate of the FET and the upper contacts, and

wherein the upper substrate defines a first contact hole, one of the upper contacts defines a second contact hole aligned with the first contact hole and the first and second contact holes cooperatively define a through-hole aligned with the stack; and
an interlayer via extending through the through-hole to communicatively couple the stack and the one of the upper contacts.

2. The circuit according to claim 1 , wherein:
the lower substrate comprises a semiconductor substrate; and
the upper substrate comprises a bonding film.

3. The circuit according to claim 1 , wherein:
the FET of the lower layer comprises at least one of a planar FET, a finFET and a nanosheet FET; and
the FET of the upper layer comprises at least one of a planar FET, finFET and a nanosheet FET.

4. The circuit according to claim 1 , wherein the one of the upper contacts comprises at least one of merged epitaxial contacts, un-merged epitaxial contacts, a planar epitaxial contact, non-epitaxial fins and a non-epitaxial planar device.

5. The circuit according to claim 1 , wherein the interlayer via comprises an electrically conductive material.

6. The circuit according to claim 1 , wherein the upper and lower layers are adjacent.

7. The circuit according to claim 1 further comprising intermediate layers interposed between the upper and lower layers.

8. An integrated circuit comprising:
a lower layer comprising a lower substrate, lower electronic devices, metallization elements and contact elements;
wherein one of the lower electronic devices comprises:
a field effect transistor (FET) comprising a gate,
lower contacts comprising complementary source or drain epitaxial contacts, and
spacers interposed between the gate of the FET and the lower contacts;

wherein at least one of the contact elements is communicatively coupled between a metallization element and one of the lower contacts to form a stack;
an upper layer comprising an upper substrate and upper electronic devices;
wherein one of the upper electronic devices comprises:
a nanosheet FET comprising a gate,
epitaxial contacts grown on sides of the nanosheet FET, and
spacers interposed between the gate of the nanosheet FET and the epitaxial contacts;

wherein the upper substrate defines a through-hole aligned with the stack and the epitaxial contacts such that the epitaxial contacts extend into the through-hole; and
an interlayer via extending through the through-hole to communicatively couple the stack and the epitaxial contacts extending into the through-hole.

9. The circuit according to claim 8 , wherein the epitaxial contacts are merged.

10. The circuit according to claim 8 , wherein the epitaxial contacts are unmerged.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Clevenger Lawrence A
• Hook Terence B
• Rubin Joshua M
• Yamashita Tenko

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title

• H10P50/283

  by chemical means · CPC title