Monolithic three-dimensional (3D) ICs with local inter-level interconnects

Patent metadata

Field	Value
Publication number	US-9685436-B2
Application number	US-201314778512-A
Country	US
Kind code	B2
Filing date	Jun 25, 2013
Priority date	Jun 25, 2013
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

First claim

What is claimed is:

1. A vertically integrated microelectronic device comprising:
a first transistor including a first semiconductor body extending laterally within a first transistor level;
a second transistor including:
a second semiconductor body extending laterally within a second transistor level over the first transistor level and separated from the first transistor level by one or more inter-level dielectric layers; and
a gate electrode disposed over a channel region between a source region and a drain region of the second semiconductor body, wherein the gate electrode is separated from the channel region by a gate dielectric layer; and an inter-level interconnect making ohmic contact with at least a sidewall of the gate electrode, making direct physical contact with the gate dielectric layer, extending below the gate dielectric layer and through at least one of the one or more inter-level dielectric layers, and electrically coupling with a terminal of the first transistor.

2. The device of claim 1 , wherein:
the second semiconductor body comprises a fin; and further comprising
a second inter-level interconnect contacting at least one sidewall of a source or drain region of the fin.

3. The device of claim 2 , wherein:
the second inter-level interconnect is contacting at least two opposing sidewalls of the source or drain region of the fin, and electrically couples with a source or drain terminal of the first semiconductor body.

4. The device of claim 3 , wherein:
the second inter-level interconnect electrically couples with the source or drain terminal through an intervening interconnect metallization located between the first and second transistor levels; and
the inter-level interconnect electrically interconnects with a transistor in the first transistor level through another intervening interconnect metallization located between the first second transistor levels.

5. The device of claim 1 , wherein
the inter-level interconnect electrically couples with the terminal through a first intervening interconnect metallization located between the first and second transistor levels.

6. The device of claim 1 , wherein
the inter-level interconnect is contacting at least one sidewall of the gate electrode.

7. The device of claim 1 , wherein the inter-level interconnect is separated from a sidewall of a channel region of the second semiconductor body by only the gate dielectric, with the inter-level interconnect operable as a gate electrode of the second transistor.

8. The device of claim 1 , wherein the gate dielectric is further disposed between the inter-level interconnect and at least one of the one or more inter-level dielectric layers.

9. The device of claim 1 , wherein the inter-level interconnect is in direct contact with at least one of the one or more inter-level dielectric layers.

10. A monolithic three dimensional (3D) SRAM cell, comprising:
two load transistors disposed on a first transistor level;
two drive transistors and two pass-gate transistors disposed on a second transistor level over the first transistor level, with an inter-level dielectric layer disposed there between;
a first inter-level interconnect contacting at least two opposing sidewalls of a semiconductor drain region of a first of the drive transistors and extending through the inter-level dielectric layer;
a second inter-level interconnect contacting at least two opposing sidewalls of a semiconductor drain region of a second of the drive transistors and extending through the inter-level dielectric layer;
a third inter-level interconnect in direct physical contact with a gate dielectric of the first of the drive transistors and extending through the inter-level dielectric layer;
a fourth inter-level interconnect in direct physical contact with a gate dielectric of the second of the drive transistors and extending through the inter-level dielectric layer; wherein:
the first inter-level interconnect electrically couples to a drain terminal of the first of the two load transistors;
the second inter-level interconnect electrically couples to a drain terminal of the second of the two load transistors;
the third inter-level interconnect electrically couples to a gate electrode of the first of the two load transistors; and
the fourth inter-level interconnect electrically couples a gate electrode of the second of the two load transistors.

11. The 3D SRAM cell of claim 10 , wherein:
the load and drive transistors comprise laterally-oriented fins having semiconductor channel regions adjacent to the semiconductor drain regions; and
the inter-level interconnects extend vertically through the inter-level dielectric layer, substantially orthogonal to the laterally-oriented fins.

12. The 3D SRAM cell of claim 10 , wherein:
each of the first and second inter-level interconnects contacts a separate intervening interconnect metallization located between the first the second transistor levels; and
each of the third and fourth inter-level interconnects is disposed along at least one sidewall of the gate electrode or at least one sidewall of a semiconductor channel region of one of the drive transistors, and contacts a separate intervening interconnect metallization located between the first and the second transistor levels.

13. A microprocessor comprising:
an SRAM cache memory, wherein the SRAM cache memory further comprises the 3D SRAM cell of claim 10 .

14. A mobile computing platform comprising:
the microprocessor of claim 13 ;
a display screen communicatively coupled to the microprocessor; and
a wireless transceiver communicatively coupled to the microprocessor.

15. A method of fabricating a vertically integrated microelectronic device, the method comprising:
receiving a first transistor within a first transistor level;
forming a second transistor over the first transistor with one or more inter-level dielectric layers there between; and
interconnecting the first and second transistors by:
etching an inter-level via that:
intersects a gate dielectric layer that extends over a semiconductor channel region of the second transistor;
extends through at least one of the one or more inter-level dielectric layers; and
exposes a conductive via land that is electrically coupled to the first transistor; and

depositing an inter-level interconnect in the inter-level via, wherein metal of the inter-level interconnect contacts both the via land and the gate dielectric layer.

16. The method of claim 15 , wherein:
the semiconductor channel region is a portion of a semiconductor fin;
etching the inter-level via exposes at least one fin sidewall or a portion of the gate dielectric layer covering at least one fin sidewall;
depositing the inter-level interconnect further comprises depositing gate electrode metallization over the gate dielectric layer on at least the fin sidewall; and
the via land is a portion of an interconnect metallization contacting at least one of a gate electrode or a semiconductor source or drain region of the first transistor.

17. The method of claim 15 , wherein:
the semiconductor channel region is a portion of a semiconductor fin;
etching the inter-level via exposes a top and two opposing fin sidewalls and further exposes a portion of an intra-level interconnect metallization contacting a semiconductor channel region of the first transistor; and
depositing the inter-level interconnect further comprises depositing a gate electrode metallization onto the fin top, on the two fin sidewalls, and on the exposed portion of the intra-level interco

Assignees

• Intel Corp

Inventors

• Morrow Patrick
• Jun Kimin
• Webb M Clair
• Nelson Donald W

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/01

  Manufacture or treatment · CPC title