Uniform electrochemical plating of metal onto arrays of pillars having different lateral densities and related technology

Patent metadata

Field	Value
Publication number	US-11923329-B2
Application number	US-202218079183-A
Country	US
Kind code	B2
Filing date	Dec 12, 2022
Priority date	Dec 15, 2016
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.

First claim

I claim:

1. A semiconductor die assembly, comprising:
a first semiconductor die having a major surface with non-overlapping first and second regions;
a second semiconductor die spaced apart from the first semiconductor die;
an array of first pillars extending from the first region of the major surface of the first semiconductor die to the second semiconductor die and electrically coupling the first and second semiconductor dies; and
an array of second pillars extending from the second region of the major surface of the first semiconductor die toward the second semiconductor die, wherein the second pillars are electrically insulated from one or both of the first and second semiconductor dies,
wherein—
a minimum lateral spacing between the first pillars is different than a minimum lateral spacing between the second pillars by at least 5%, or
an average width of the first pillars is different than an average width of the second pillars by at least 2%.

2. The semiconductor die assembly of claim 1 wherein:
the minimum lateral spacing between the first pillars is lower than the minimum lateral spacing between the second pillars; or
the average width of the first pillars is greater than the average width of the second pillars.

3. The semiconductor die assembly of claim 1 wherein:
the minimum lateral spacing between the first pillars is lower than the minimum lateral spacing between the second pillars; or
the average width of the first pillars is less than the average width of the second pillars.

4. The semiconductor die assembly of claim 1 wherein the second pillars are configured to carry heat between the first and second semiconductor dies.

5. The semiconductor die assembly of claim 1 wherein the minimum lateral spacing between the first pillars is different than the minimum lateral spacing between the second pillars by at least 10%.

6. The semiconductor die assembly of claim 5 wherein the average width of the first pillars is different than the average width of the second pillars by at least 5%.

7. A semiconductor die assembly, comprising:
a first semiconductor die having a major surface with a first region and a second region discrete from the first region;
a second semiconductor die spaced apart from the first semiconductor die;
an array of first pillars extending between the first region of the major surface of the first semiconductor die to the second semiconductor die; and
dummy pillars interspersed among the first pillars,
wherein—
a minimum lateral spacing between the first pillars is different than a minimum lateral spacing between the dummy pillars by at least 5%, or
an average height of the dummy pillars is at least 10% less than an average height of the first pillars.

8. The semiconductor die assembly of claim 7 wherein an average width of the first pillars is different than an average width of the dummy pillars by at most 3%.

9. The semiconductor die assembly of claim 7 wherein:
the first pillars are configured to electrically couple the first and second semiconductor dies; and
the dummy pillars are electrically insulated from one or both of the first and second semiconductor dies.

10. The semiconductor die assembly of claim 7 , further comprising volumes of solder respectively disposed between the respective first pillars and the second semiconductor die.

11. The semiconductor die assembly of claim 10 , further comprising bond pads respectively disposed between the respective volumes of solder and the second semiconductor die.

12. The semiconductor die assembly of claim 7 wherein:
the dummy pillars are first dummy pillars;
the semiconductor die assembly further comprises second dummy pillars;
a minimum lateral spacing between the first dummy pillars and the first pillars is less than a minimum lateral spacing between the second dummy pillars and the first pillars; and
an average width of the second dummy pillars is less than an average width of the first dummy pillars.

13. The semiconductor die assembly of claim 12 wherein an average height of the second dummy pillars is less than an average height of the first dummy pillars.

14. The semiconductor die assembly of claim 12 wherein the minimum lateral spacing between the first dummy pillars is different than the minimum lateral spacing between the second dummy pillars by at least 10%.

15. A method for making a semiconductor die assembly, the method comprising:
electrochemically plating metal by an electrochemical plating process onto an array of first pillars extending from a first region of a major surface of a semiconductor die; and
simultaneously electrochemically plating metal by the electrochemical plating process onto an array of second pillars extending from a non-overlapping second region of the major surface of the semiconductor die,
wherein—
a difference between a minimum lateral spacing between the first pillars and a minimum lateral spacing between the second pillars has a first effect on relative metal deposition rates of the electrochemical plating process at the first and second regions of the major surface of the semiconductor die, or
a difference between an average width of the first pillars and an average width of the second pillars has a second effect on the relative metal deposition rates of the electrochemical plating process at the first and second regions of the major surface of the semiconductor die.

16. The method of claim 15 , further comprising forming respective patterns for the arrays of first and second pillars by photolithography.

17. The method of claim 15 wherein:
the semiconductor die is a first semiconductor die; and
the method further comprises—
electrically coupling the first semiconductor die to a second semiconductor die via the first pillars, and
thermally coupling the first semiconductor die to the second semiconductor die via the second pillars.

18. The method of claim 17 wherein electrically coupling the first semiconductor die to the second semiconductor die via the first pillars includes electrically coupling the first semiconductor die to the second semiconductor die via the first pillars and via solder between the first pillars and the second semiconductor die.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Hacker Jonathan S

Classifications

• H10W72/07254

  changes in dispositions · CPC title

• H10W72/07252

  changes in structures or sizes · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/267

  Multiple bump connectors having different functions · CPC title

• H10W72/265

  Providing thermal transfer, e.g. thermal bumps · CPC title