Package structures and methods of forming the same

US9564416B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9564416-B2
Application numberUS-201514696054-A
CountryUS
Kind codeB2
Filing dateApr 24, 2015
Priority dateFeb 13, 2015
Publication dateFeb 7, 2017
Grant dateFeb 7, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Packages structure and methods of forming them are discussed. A structure includes a first die, a first encapsulant at least laterally encapsulating the first die, and a redistribution structure on the first die and the first encapsulant. The second die is attached by an external electrical connector to the redistribution structure. The second die is on an opposite side of the redistribution structure from the first die. A second encapsulant is on the redistribution structure and at least laterally encapsulates the second die. The second encapsulant has a surface distal from the redistribution structure. A conductive feature extends from the redistribution structure through the second encapsulant to the surface of the second encapsulant. A conductive pillar is on the conductive feature, and the conductive pillar protrudes from the surface of the second encapsulant.

First claim

Opening claim text (preview).

What is claimed is: 1. A structure comprising: a first die having a first active side; a first encapsulant at least laterally encapsulating the first die; a redistribution structure on the first encapsulant and the first active side of the first die; a second die having a second active side, the second active side of the second die being attached by a first external electrical connector to the redistribution structure, the second die being on an opposite side of the redistribution structure from the first die; a second encapsulant on the redistribution structure and at least laterally encapsulating the second die, the second encapsulant having a first surface distal from the redistribution structure; a conductive feature extending from the redistribution structure through the second encapsulant to the first surface of the second encapsulant; and a first conductive pillar on the conductive feature, the first conductive pillar protruding from the first surface of the second encapsulant. 2. The structure of claim 1 , wherein the conductive feature is a second conductive pillar extending from the redistribution structure to the first surface of the second encapsulant. 3. The structure of claim 1 , wherein the conductive feature comprises a second conductive pillar on the redistribution structure and a via extending from the second conductive pillar to the first surface of the second encapsulant. 4. The structure of claim 3 , wherein the via is defined by an opening extending from the first surface of the second encapsulant to the second conductive pillar, the via comprising a conductive material fully filling the opening. 5. The structure of claim 3 , wherein the via comprises a conductive material and a filler material different from the conductive material. 6. The structure of claim 1 , wherein the first external electrical connector comprises a second conductive pillar on the redistribution structure, and the conductive feature comprises a third conductive pillar on the redistribution structure, a first width of the second conductive pillar being less than a second width of the third conductive pillar. 7. The structure of claim 1 , wherein the first conductive pillar is attached to a substrate by solder. 8. The structure of claim 1 , wherein the second die is one of a stack of dies. 9. A structure comprising: a package component comprising a redistribution structure on an encapsulated first die; first conductive pillars on the redistribution structure at least laterally encapsulated by a first encapsulant; a second die on the redistribution structure at least laterally encapsulated by the first encapsulant, the first encapsulant having a first surface distal from the redistribution structure; and second conductive pillars protruding from the first surface of the first encapsulant, each of the second conductive pillars being electrically coupled to a respective one of the first conductive pillars, wherein the second conductive pillars protrude from the first surface of the first encapsulant such that opposing sidewalls of the second conductive pillars are uncovered by the first encapsulant. 10. The structure of claim 9 , wherein the first conductive pillars extend from the redistribution structure to the first surface of the encapsulant. 11. The structure of claim 9 further comprising vias in the first encapsulant, each via extending from a respective one of the first conductive pillars to a respective one of the second conductive pillars. 12. The structure of claim 11 , wherein each via comprises a conductive material and a filler material different from the conductive material, the conductive material at least laterally surrounding the filler material. 13. The structure of claim 9 , wherein the second die is attached to the redistribution structure using third conductive pillars, a width of the third conductive pillars being less than a width of the first conductive pillars. 14. The structure of claim 9 , wherein the second die is one of stacked dies. 15. A method comprising: encapsulating a first die with a first encapsulant; forming a redistribution structure on the first die and the first encapsulant; forming a first conductive pillar on the redistribution structure and in a central region of the redistribution structure; forming a second conductive pillar on the redistribution structure and in a periphery region of the redistribution structure, a width of the first conductive pillar being less than a width of the second conductive pillar; attaching a second die to the redistribution structure using the first conductive pillar; at least laterally encapsulating the second die and the second conductive pillar with a second encapsulant; and after encapsulating the second die and the second conductive pillar, forming a third conductive pillar electrically coupled to the second conductive pillar. 16. The method of claim 15 , wherein each of the forming the first conductive pillar, the forming the second conductive pillar, and the forming the third conductive pillar comprises using a plating process. 17. The method of claim 15 , wherein the third conductive pillar is formed directly on the second conductive pillar. 18. The method of claim 15 further comprising: forming an opening through the encapsulant exposing the second conductive pillar; and forming a via in the openings, the via comprising a conductive material, the third conductive pillar being formed directly on the via. 19. The method of claim 18 , wherein the conductive material completely fills the opening. 20. The method of claim 18 , wherein the forming the via comprises: forming the conductive material along a sidewall surface of the opening and a bottom surface of the opening, wherein an unfilled portion of the opening remains unfilled; and forming a filler material in the unfilled portion of the opening, the filler material being a different material than the conductive material.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between stacked chips · CPC title

  • characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

  • the encapsulations exposing the passive side of the semiconductor body · CPC title

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What does patent US9564416B2 cover?
Packages structure and methods of forming them are discussed. A structure includes a first die, a first encapsulant at least laterally encapsulating the first die, and a redistribution structure on the first die and the first encapsulant. The second die is attached by an external electrical connector to the redistribution structure. The second die is on an opposite side of the redistribution st…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W74/01. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 07 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).