Via interconnects including super vias

Patent metadata

Field	Value
Publication number	US-11916013-B2
Application number	US-202117465815-A
Country	US
Kind code	B2
Filing date	Sep 2, 2021
Priority date	Sep 2, 2021
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

Interconnect structures including super vias are formed during back-end-of-line processing using sacrificial placeholders to protect the bottom portions of the super vias while upper portions of the super vias are formed. The sacrificial placeholders are removed and replaced by metal conductors that fill the bottom and upper portions of the super vias.

First claim

What is claimed is:

1. An interconnect structure comprising:
a first interconnect layer including a first dielectric layer and a first metal layer;
a second interconnect layer including a second dielectric layer and a second metal layer;
a first dielectric cap layer between the first interconnect layer and the second interconnect layer;
a placeholder via extending through the second interconnect layer and the first dielectric cap layer, the placeholder via containing sacrificial placeholder material;
a second dielectric cap layer over the second dielectric layer;
a patterned third dielectric layer over the second dielectric cap layer, the patterned third dielectric layer including an upper super via portion vertically aligned with the placeholder via, the placeholder via comprising a bottom super via portion, the bottom super via portion and the upper super via portion providing portions of a super via extending from the third dielectric layer to the first interconnect layer.

2. The interconnect structure of claim 1 , wherein the sacrificial placeholder material comprises an organic planarization layer.

3. The interconnect structure of 1 , wherein the sacrificial placeholder material comprises titanium nitride or tungsten.

4. The interconnect structure of claim 1 , wherein the placeholder via extends through the second cap layer.

5. The interconnect structure of claim 1 , wherein the second dielectric cap layer covers the sacrificial placeholder material within the placeholder via.

Assignees

• IBM

Inventors

• Mignot Yann
• Waskiewicz Christopher J
• Miller Eric
• Park Chanro

Classifications

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title