Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs)

Patent metadata

Field	Value
Publication number	US-10354912-B2
Application number	US-201615229535-A
Country	US
Kind code	B2
Filing date	Aug 5, 2016
Priority date	Mar 21, 2016
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for integrated circuits (ICs) is disclosed. To reduce or avoid misalignment of a via to an underlying, interconnected metal line, vias are fabricated in the interconnect structure to be self-aligned with an underlying, interconnected metal line. In this regard, underlying metal lines are formed in a dielectric layer. A recess is formed in an underlying metal line below a top surface of an inter-layer dielectric. A stop layer is disposed above the inter-layer dielectric and within the recess of the underlying metal line. The stop layer allows a via tunnel to be formed (e.g., etched) down within the recess of the underlying metal line to self-align the via tunnel with the underlying metal line. A conductive material is then deposited in the via tunnel extending into the recess to form the self-aligned via interconnected to the underlying metal line.

First claim

What is claimed is:

1. An interconnect structure for an integrated circuit (IC), comprising: an underlying metal layer, comprising:
a plurality of underlying metal lines disposed in a dielectric layer having a top surface, the plurality of underlying metal lines comprising an underlying metal line and an adjacent underlying metal line adjacent to the underlying metal line;
a recess area of a recess width disposed in the dielectric layer below the top surface of the dielectric layer of a recess distance down to a top surface of the underlying metal line among the plurality of underlying metal lines;
an adjacent recess area having an adjacent recess area width defined by a first side surface to a second side surface of the adjacent recess area disposed in the dielectric layer below the top surface of the dielectric layer of the recess distance down to a top surface of the adjacent underlying metal line; and
an etch stop layer disposed in the adjacent recess area on the top surface of the adjacent underlying metal line and on the first and the second side surfaces of the adjacent recess area forming a cavity in the adjacent recess area having a cavity width less than the adjacent recess area width, wherein a portion of the etch stop layer is disposed on the top surface of the dielectric layer, the etch stop layer comprises a semiconductor;
an overlying metal layer disposed above the underlying metal layer, the overlying metal layer comprising a plurality of overlying metal lines;
a second dielectric layer comprising:
a first dielectric material portion disposed below the top surface of the dielectric layer and in the cavity of the adjacent recess area; and
a second dielectric material portion disposed between the overlying metal layer and the portion of the etch stop layer disposed on the top surface of the dielectric layer; and
a self-aligned via of a via opening width disposed through the second dielectric layer between the underlying metal layer and the overlying metal layer and electrically interconnecting the underlying metal line to an overlying metal line among the plurality of overlying metal lines, wherein the self-aligned via comprises:
a first via portion of the self-aligned via extending into the recess area of the underlying metal line to be self-aligned with the underlying metal line; and
a second via portion of the self-aligned via extending outside of the recess area of the via opening width.

2. The interconnect structure of claim 1 , wherein the second via portion of the self-aligned via has a width greater than the recess width of the recess area.

3. The interconnect structure of claim 1 , wherein the adjacent recess area is formed by removal of a portion of the adjacent underlying metal line below the top surface of the dielectric layer of the recess distance.

4. The interconnect structure of claim 1 , wherein the recess distance of the adjacent underlying metal line is at least approximately one-half (½) of a metal pitch of the plurality of underlying metal lines.

5. The interconnect structure of claim 1 , wherein the recess area is formed by removal of a portion of the underlying metal line below the top surface of the dielectric layer of the recess distance.

6. The interconnect structure of claim 1 , wherein the recess distance of the underlying metal line is at least approximately one-half (½) of a metal pitch of the plurality of underlying metal lines.

7. The interconnect structure of claim 1 , wherein the plurality of underlying metal lines are formed from a metal material selected from the group consisting of Cobalt (Co), Ruthenium (Ru), and Aluminum (Al).

8. The interconnect structure of claim 1 , wherein a metal pitch of the plurality of underlying metal lines is less than or equal to fifty-six (56) nanometers (nm).

9. The interconnect structure of claim 1 , wherein a metal pitch of the plurality of underlying metal lines is less than or equal to twenty-eight (28) nanometers (nm).

10. The interconnect structure of claim 1 , wherein a metal pitch of the plurality of underlying metal lines is less than or equal to five (5) nanometers (nm).

11. The interconnect structure of claim 1 , wherein the etch stop layer is comprised of Aluminum Nitride (AlN).

12. The interconnect structure of claim 1 , wherein a thickness of the etch stop layer is less than or equal to two (2) nanometers (nm).

13. The interconnect structure of claim 1 integrated into the IC.

14. The interconnect structure of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a smart phone; a tablet; a phablet; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; and an automobile.

Assignees

• Qualcomm Inc

Inventors

• Xu Jeffrey Junhao
• Zhu John Jianhong
• Yeap Choh Fei

Classifications

• H10W70/635

  Through-vias · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title