Skip via structures

Patent metadata

Field	Value
Publication number	US-9805972-B1
Application number	US-201715437065-A
Country	US
Kind code	B1
Filing date	Feb 20, 2017
Priority date	Feb 20, 2017
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; an upper wiring layer with one or more wiring structures, located above the first wiring layer; a blocking material which contacts at least one of the wiring structures of the upper wiring layer; a skip via with metallization, the skip via passes through the upper wiring layer and makes contact with the one or more wiring structures of the first wiring layer; and a conductive material in the skip via above the metallization and in a via interconnect above the blocking material.

First claim

What is claimed:

1. A structure, comprising:
a first wiring layer with one or more wiring structures;
an upper wiring layer with one or more wiring structures, located above the first wiring layer;
a blocking material which contacts at least one of the wiring structures of the upper wiring layer;
a skip via with metallization, the skip via passes through the upper wiring layer and makes contact with the one or more wiring structures of the first wiring layer; and
a conductive material in the skip via above the metallization and in a via interconnect above the blocking material.

2. The structure of claim 1 , wherein the conductive material is part of the skip via and a wiring structure above the skip via.

3. The structure of claim 2 , wherein the metallization is cobalt or nickel selectively grown in a via opening which passes through the upper wiring layer and which exposes the one or more wiring structures of the first wiring layer.

4. The structure of claim 3 , wherein the cobalt or nickel partially fills the via opening.

5. The structure of claim 4 , wherein the skip via is devoid of voids.

6. The structure of claim 4 , wherein the cobalt or nickel partially fills a via above the blocking material.

7. The structure of claim 6 , wherein the conductive material fills a wiring trench above the via and the upper wiring layer, and the conductive material forms a wiring structure.

8. The structure of claim 1 , wherein the blocking material is Mn.

9. The structure of claim 1 , wherein the blocking material is CuSi or CuGe, formed by treating a Cu surface of the wiring structure of the upper wiring layer with SiH 4 or GeH 4 , respectively.

10. A method, comprising:
forming a via to expose one or more wiring structures of an upper wiring layer;
forming a skip via which passes through the upper wiring layer and which exposes one or more wiring structures of a lower wiring layer;
forming a blocking material in the via which covers the exposed one or more wiring structures of the upper wiring layer;
selectively growing metal material in the skip via; and
filling remaining portions of the skip via and the via with conductive material.

11. The method of claim 10 , wherein the selective growth of the metal material comprises selectively growing cobalt in the skip via to partially fill the skip via.

12. The method of claim 11 , wherein the selective growth of the cobalt or nickel is an electroless growth process.

13. The method of claim 12 , wherein the electroless growth process is from a bottom upwards within the skip via, starting from an exposed portion of the one or more wiring structures of the lower wiring layer.

14. The method of claim 10 , wherein the conductive material is copper.

15. The method of claim 10 , wherein the growth of the cobalt or nickel partially fills the via and the method further comprises filling remaining portions of the via and wiring trenches above the upper wiring layer with the conductive material.

16. The method of claim 10 , wherein the blocking material is formed by a deposition of Mn.

17. The structure of claim 10 , wherein the blocking material is CuSi or CuGe, formed by treating a surface of the wiring structure of the upper wiring layer with SiH 4 or GeH 4 , respectively.

18. A method, comprising:
forming a wiring layer with one or more wiring structures in a lower wiring layer;
forming a wiring layer with one or more wiring structures in an upper wiring layer, located above the lower wiring layer;
forming a first via to expose the one or more wiring structures of the upper wiring layer and a second via which passes through the upper wiring layer and which ends above the lower wiring layer;
forming a blocking material in the first via to block the exposed one or more wiring structures of the upper wiring layer;
extending the second via landing on the lower wiring layer to form a skip via exposing the one or more wiring structures of the lower wiring layer, while the blocking material protects the exposed one or more wiring structures of the upper wiring layer;
filling at least the skip via with conductive material to contact the one or more wiring structures of the lower wiring layer and in electrical connection with the one or more wiring structures of the upper wiring layer; and
filling remaining portions of the skip via and the first via with a different conductive material.

19. The method of claim 18 , wherein the blocking material is Mn, CuSi or CuGe.

20. The method of claim 18 , wherein the filling of the at least the skip via with conductive material is an electroless growth process of cobalt or nickel.

Assignees

• Globalfoundries Inc

Inventors

• Zhang Xunyuan
• Lin Sean Xuan
• Mcmahon James Jay
• Law Shao Beng

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/421

  Skip vias, i.e. vias that do not connect all metallization layers that they pass through · CPC title

• H10P14/46

  using a liquid · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title