Memory circuit architecture

Patent metadata

Field	Value
Publication number	US-11908537-B2
Application number	US-202318163146-A
Country	US
Kind code	B2
Filing date	Feb 1, 2023
Priority date	Dec 29, 2020
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component;
wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit;
wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits, wherein there is a first axis between the first quadrant and the second quadrant about which the first set of input output circuits and the second set of input output circuits are symmetrical; and
wherein a third quadrant of the plurality of quadrants includes a third bit cell core and a third set of input output circuits, the third quadrant being symmetrical with the first quadrant along a second axis that is perpendicular to a direction of wordlines in the first bit cell core.

2. The semiconductor device of claim 1 , wherein the first set of input output circuits comprises:
a first plurality of global input data paths, a first plurality of global output data paths, a first plurality of input latches coupled to the first plurality of global input data paths, and first output logic coupled to the first plurality of global data output paths.

3. The semiconductor device of claim 2 , wherein the second set of input output circuits comprises:
a second plurality of global input data paths, a second plurality of global output data paths, a second plurality of input latches coupled to the second plurality of global input data paths, and second output logic coupled to the second plurality of global data output paths.

4. The semiconductor device of claim 2 , wherein the first set of input output circuits further comprises:
a first plurality of local data paths configured to access the first bit cell core and a first plurality of sense amplifiers coupled to the first plurality of local data paths.

5. The semiconductor device of claim 4 , wherein the first axis is parallel to the direction of wordlines in the first bit cell core.

6. The semiconductor device of claim 1 , wherein the bank control component is coupled to four quadrants of the plurality of quadrants through a plurality of local bank controller circuits.

7. The semiconductor device of claim 6 , wherein the bank control component is asymmetrical about the first axis.

8. The semiconductor device of claim 1 , wherein the first bit cell core and the second bit cell core are symmetrical about the first axis.

9. The semiconductor device of claim 1 , further comprising:
a row decoder placed between the first quadrant and the third quadrant and adjacent the bank control component.

10. The semiconductor device of claim 1 , wherein the plurality of quadrants comprises:
a fourth quadrant of the plurality of quadrants, which includes a fourth bit cell core and a fourth set of input output circuits, the fourth set of input output circuits being symmetrical with the third set of input output circuits along the first axis.

11. The semiconductor device of claim 10 , further comprising:
a row decoder placed between the second quadrant and the fourth quadrant and adjacent the bank control component.

12. A system on chip (SOC) comprising:
a random-access memory (RAM) device comprising a plurality of quadrants arranged around corners of a rectangular shape of the RAM device;
wherein a first quadrant of the plurality of quadrants is defined by a first boundary that encloses portions of two perpendicular edges of the RAM device, wherein the first quadrant includes a first bit cell core and a first set of input output circuits;
wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits, and wherein there is a first axis between the first quadrant and the second quadrant about which the first set of input output circuits and the second set of input output circuits are symmetrical; and
wherein a third quadrant of the plurality of quadrants includes a third bit cell core and a third set of input output circuits, the third quadrant being symmetrical with the first quadrant along a second axis that is perpendicular to the first axis.

13. The SOC of claim 12 , wherein the second axis is perpendicular to a direction of wordlines in the first bit cell core.

14. The SOC of claim 13 , wherein the first axis is perpendicular to a direction of bitlines in the first bit cell core.

15. The SOC of claim 12 , further comprising a bank control component, common to each of the plurality of quadrants, wherein the bank control component is internally asymmetrical.

16. The SOC of claim 15 , wherein the bank control component is coupled to each quadrant of the plurality of quadrants through a plurality of local bank controller circuits.

17. The SOC of claim 12 , wherein the second quadrant is adjacent the first quadrant, and wherein a border between the first quadrant and the second quadrant defines the first axis.

18. The SOC of claim 12 , wherein the first quadrant and the third quadrant are separated by a row decoder having a plurality of wordline drivers, wherein the second axis bisects the row decoder.

19. The SOC of claim 12 , wherein a fourth quadrant of the plurality of quadrants is symmetrical with respect to the third quadrant about the first axis.

20. The SOC of claim 19 , wherein the fourth quadrant is separated from the second quadrant by a row decoder, wherein the second quadrant and the fourth quadrant are symmetrical the second axis, and wherein the second axis bisects the row decoder.

21. A semiconductor Random Access Memory (RAM) device comprising:
a first quadrant including first means for storing data and a first set of input output circuits configured to access the first data storing means, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the semiconductor RAM device;
a second quadrant including second means for storing data and a second set of input output circuits configured to access the second data storing means, wherein the first set of input output circuits and the second set of input output circuits are symmetrical about a first axis;
a third quadrant including third means for storing data and a third set of input output circuits configured to access the third data storing means, wherein the first quadrant and the third quadrant are symmetrical about a second axis perpendicular to the first axis; and
a fourth quadrant including fourth means for storing data and a fourth set of input output circuits configured to access the fourth data storing means, wherein the third quadrant and the fourth quadrant are symmetrical about the first axis.

22. The semiconductor RAM device of claim 21 , wherein the second axis bisects a row decoder placed between the first quadrant and the third quadrant.

23. The semiconductor RAM device of claim 21 , further comprising means for pre-decoding address signals, wherein the means for pre-decoding address signals are placed in a center of the semiconductor RAM device and are surrounded by the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant.

24. The semiconductor RAM device of claim 23 , wherein the means for pre-decoding address signal

Assignees

• Qualcomm Inc

Inventors

• Li David
• Biradar Rahul
• Manakkam Veetil Biju
• Chen Po-Hung
• Paul Ayan
• Son Sung
• Kushwaha Shivendra
• Chekkera Ravindra Reddy
• Yang Derek

Classifications

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title