Memory device, driving method thereof, semiconductor device, electronic component, and electronic device

Patent metadata

Field	Value
Publication number	US-10388364-B2
Application number	US-201715695128-A
Country	US
Kind code	B2
Filing date	Sep 5, 2017
Priority date	Sep 12, 2016
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

A memory device includes a memory cell, a replica cell, a read circuit, a write wordline, a read wordline, a dummy read wordline, a write bitline, a read bitline, a reference bitline, a sourceline, and a first wiring. The memory cell is electrically connected to the write wordline, the read wordline, the write bitline, the read bitline, and the sourceline. The read circuit outputs a potential based on the result of comparing the potential of the reference bitline and the potential of the read bitline. The replica cell includes a first transistor and a second transistor. The first transistor and the second transistor are electrically connected to each other in series between the bitline and the sourceline. A gate of the first transistor and a gate of the second transistor are electrically connected to a dummy read wordline and the first wiring, respectively.

First claim

The invention claimed is:

1. A memory device comprising:
a first cell;
a second cell;
a third cell;
a fourth cell;
a read circuit;
a first wordline;
a second wordline;
a third wordline;
a first bitline;
a second bitline;
a third bitline;
a fourth bitline;
a fifth bitline;
a sixth bitline;
a first sourceline;
a second sourceline; and
a first wiring,
wherein the first cell includes a first transistor and a second transistor,
wherein a gate, a first terminal, and a second terminal of the first transistor are electrically connected to the third wordline, the third bitline, and a first terminal of the second transistor, respectively,
wherein a gate and a second terminal of the second transistor are electrically connected to the first wiring and the first sourceline, respectively,
wherein the second cell includes a third transistor, a fourth transistor, and a first capacitor,
wherein a gate, a first terminal, and a second terminal of the third transistor are electrically connected to the first wordline, the first bitline, and a gate of the fourth transistor, respectively,
wherein a first terminal and a second terminal of the first capacitor are electrically connected to the gate of the fourth transistor and the second wordline, respectively,
wherein a first terminal and a second terminal of the fourth transistor are electrically connected to the first sourceline and the second bitline, respectively,
wherein the third cell includes a fifth transistor and a sixth transistor,
wherein a gate, a first terminal, and a second terminal of the fifth transistor are electrically connected to the third wordline, the sixth bitline, and a first terminal of the sixth transistor, respectively,
wherein a gate and a second terminal of the sixth transistor are electrically connected to the first wiring and the second sourceline, respectively,
wherein the fourth cell includes a seventh transistor, an eighth transistor, and a second capacitor,
wherein a gate, a first terminal, and a second terminal of the seventh transistor are electrically connected to the first wordline, the fourth bitline, and a gate of the eighth transistor, respectively,
wherein a first terminal and a second terminal of the second capacitor are electrically connected to the gate of the eighth transistor and the second wordline, respectively,
wherein a first terminal and a second terminal of the eighth transistor are electrically connected to the second sourceline and the fifth bitline, respectively,
wherein the first transistor, the second transistor, and the fourth transistor are the same in conductivity type, and
wherein the read circuit compares a potential of the third bitline with a potential of the second bitline and outputs a potential based on the comparison result.

2. The memory device according to claim 1 , wherein a channel formation region of the third transistor includes a metal oxide.

3. A semiconductor device comprising:
a processor core;
a memory portion; and
a bus,
wherein the memory portion comprises the memory device according to claim 1 , and
wherein a signal and data are transferred between the processor core and the memory portion through the bus.

4. The semiconductor device according to claim 3 ,
wherein the memory portion includes at least one of a DRAM, an SRAM, a flash memory, a ferroelectric RAM, a magnetoresistive RAM, a resistance RAM, and a phase change RAM.

5. A memory device comprising:
a first memory cell array;
a second memory cell array; and
a column circuit,
the first memory cell array comprising:
a first cell;
a second cell;
a first wordline;
a second wordline;
a third wordline;
a first bitline;
a second bitline;
a first sourceline; and
a first wiring,

the second memory cell array comprising:
a third cell;
a fourth cell;
a fourth wordline;
a fifth wordline;
a sixth wordline;
a third bitline;
a fourth bitline;
a second sourceline; and
a second wiring,

wherein the column circuit is electrically connected to the first bitline, the second bitline, the first sourceline, the third bitline, the fourth bitline, and the second sourceline,
wherein the column circuit includes a sense amplifier, a first circuit, a second circuit, a third circuit, and a fourth circuit,
wherein the sense amplifier includes a first node and a second node,
wherein the first circuit is configured to control electrical continuity between the second bitline and the second node,
wherein the second circuit is configured to control electrical continuity between the fourth bitline and the first node,
wherein the third circuit is configured to control electrical continuity between the first bitline and the first node,
wherein the fourth circuit is configured to control electrical continuity between the third bitline and the second node,
wherein the first cell includes a first transistor and a second transistor,
wherein a gate, a first terminal, and a second terminal of the first transistor are electrically connected to the third wordline, the second bitline, and a first terminal of the second transistor, respectively,
wherein a gate and a second terminal of the second transistor are electrically connected to the first wiring and the first sourceline, respectively,
wherein the third cell includes a third transistor and a fourth transistor,
wherein a gate, a first terminal, and a second terminal of the third transistor are electrically connected to the sixth wordline, the fourth bitline, and a first terminal of the fourth transistor, respectively,
wherein a gate and a second terminal of the fourth transistor are electrically connected to the second wiring and the second sourceline, respectively,
wherein the second cell includes a fifth transistor, a sixth transistor, and a first capacitor,
wherein a gate, a first terminal, and a second terminal of the fifth transistor are electrically connected to the first wordline, the first bitline, and a gate of the sixth transistor, respectively,
wherein a first terminal and a second terminal of the first capacitor are electrically connected to the gate of the sixth transistor and the second wordline, respectively,
wherein a first terminal and a second terminal of the sixth transistor are electrically connected to the first sourceline and the second bitline, respectively,
wherein the fourth cell includes a seventh transistor, an eighth transistor, and a second capacitor,
wherein a gate, a first terminal, and a second terminal of the seventh transistor are electrically connected to the fourth wordline, the third bitline, and a gate of the eighth transistor, respectively,
wherein a first terminal and a second terminal of the second capacitor are electrically connected to the gate of the eighth transistor and the fifth wordline, respectively,
wherein a first terminal and a second terminal of the eighth transistor are electrically connected to the second sourceline and the fourth bitline, respectively, and
wherein the first transistor, the second transistor, the sixth transistor, and the eighth transistor are the same in conductivity type.

6. The memory device according to claim 5 , wherein a channel formation region of the seventh transistor includes a metal oxide.

7. A semiconductor device comprising:
a processor core;
a memory portion; and
a bus,
wherein the memory portion comprises the memory device according to claim 5 , and
wherein a signal and data are transferred between the processor core and the memory portion through the bus.

8. The semiconductor device according to claim 7 ,
wherein the memory portion includes at least one of a DRAM, an SRAM, a flash memory, a ferroelectric RAM, a magnetoresistive RAM, a resistance RAM, and

Assignees

• Semiconductor Energy Lab

Inventors

• Ishizu Takahiko
• Nagatsuka Shuhei

Classifications

• G11C11/404

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/4099

  Dummy cell treatment; Reference voltage generators · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C7/227

  Timing of memory operations based on dummy memory elements or replica circuits · CPC title