Page buffer performing memory operation
US-2024274171-A1 · Aug 15, 2024 · US
Memory macro with a voltage keeper
US8988948B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8988948-B2 |
| Application number | US-201313949664-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 24, 2013 |
| Priority date | Jul 24, 2013 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line.
First claim
Opening claim text (preview).
What is claimed is: 1. In a memory macro comprising a memory array, a plurality of first data lines associated with memory cells of the memory array, and a second data line associated with the memory array, a circuit comprising: a node coupled with the second data line; and a first switch comprising a first terminal coupled to the node, and a second terminal coupled to a first one of the first data lines, wherein the first switch is configured to electrically couple the second…
Assignees
Inventors
Classifications
Physics · mapped topic
Physics · mapped topic
- G11C7/12Primary
Physics · mapped topic
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8988948B2 cover?
- A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line.
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification G11C7/12. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).