Memory circuit architecture

Patent metadata

Field	Value
Publication number	US-11600307-B2
Application number	US-202017136616-A
Country	US
Kind code	B2
Filing date	Dec 29, 2020
Priority date	Dec 29, 2020
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component;
wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; and
wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

2. The semiconductor device of claim 1 , wherein the border is parallel to a direction of wordlines in the first bit cell core.

3. The semiconductor device of claim 1 , further comprising:
a third quadrant of the plurality of quadrants, which includes a third bit cell core and a third set of input output circuits configured to access the third bit cell core, the third quadrant being symmetrical with the first quadrant along a second axis that is perpendicular to a direction of wordlines in the first bit cell core.

4. The semiconductor device of claim 3 , further comprising:
a row decoder placed between the first quadrant and the third quadrant and adjacent the bank control component.

5. The semiconductor device of claim 3 , further comprising:
a fourth quadrant of the plurality of quadrants, which includes a fourth bit cell core and a fourth set of input output circuits configured to access the fourth bit cell core, the fourth quadrant being adjacent the third quadrant and symmetrical with the third quadrant along the first axis.

6. The semiconductor device of claim 5 , further comprising:
a row decoder placed between the second quadrant and the fourth quadrant and adjacent the bank control component.

7. The semiconductor device of claim 1 , wherein the first set of input output circuits and the second set of input output circuits are adjacent each other in the semiconductor device, further wherein the first set of input output circuits are electrically isolated from the second set of input output circuits.

8. The semiconductor device of claim 1 , wherein the first quadrant further comprises:
an additional bit cell core separated from the first bit cell core by a set of sense amplifiers configured to access the additional bit cell core.

9. The semiconductor device of claim 1 , wherein the bank control component comprises pre-decoding circuitry configured to access each quadrant of the plurality of quadrants.

10. The semiconductor device of claim 1 , wherein the memory circuit is in communication with four enable signals from outside the memory circuit.

11. A method of operating a semiconductor device, the method comprising:
performing an input or output operation on a memory circuit, including receiving an enable signal directed toward a first quadrant of a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component;
wherein the first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit;
wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical;
wherein performing the input or output operation on the memory circuit includes performing pre-decoding at the bank control component and activating word line drivers in a row decoder according to the pre-decoding.

12. The method of claim 11 , further comprising:
wherein the input or output operation comprises a read operation or a write operation.

13. The method of claim 11 , further comprising:
performing an additional input or output operation at the second bit cell core.

14. The method of claim 11 , further comprising a third quadrant, wherein the third quadrant includes a third bit cell core and a third set of input output circuits configured to access the third bit cell core, the third quadrant being separated from the first quadrant by the row decoder, wherein a second axis is perpendicular to the first axis, and wherein the first quadrant and the third quadrant are symmetrical about the second axis.

15. The method of claim 14 , further comprising:
performing an additional input or output operation at the third bit cell core.

16. The method of claim 15 , wherein the input or output operation and the additional input or output operation are performed simultaneously.

17. The method of claim 15 , wherein performing the additional input or output operation comprises:
receiving an additional enable signal directed toward the third quadrant.

18. The method of claim 15 , wherein performing the additional input or output operation comprises:
activating the word line drivers in the row decoder according to the pre-decoding.

19. A system on chip (SOC) comprising:
a random-access memory (RAM) device comprising a plurality of quadrants arranged around corners of a rectangular shape of the RAM device;
wherein a first quadrant of the plurality of quadrants is defined by a first boundary that encloses portions of two perpendicular edges of the RAM device;
wherein a second quadrant of the plurality of quadrants is horizontal axis symmetrical with respect to the first quadrant; and
wherein a third quadrant of the plurality of quadrants is vertical axis symmetrical with respect to the first quadrant.

20. The SOC of claim 19 , further comprising a bank control component, common to each of the plurality of quadrants, wherein the bank control component is internally asymmetrical.

21. The SOC of claim 19 , wherein the first quadrant comprises a first bit cell core and a first set of input output circuits.

22. The SOC of claim 19 , wherein the second quadrant is adjacent the first quadrant, and wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

23. The SOC of claim 19 , wherein the first quadrant and the third quadrant are separated by a row decoder having a plurality of word line drivers, wherein the first quadrant and the third quadrant are symmetrical about a vertical axis bisecting the row decoder.

24. The SOC of claim 19 , wherein a fourth quadrant of the plurality of quadrants is horizontal axis symmetrical with respect to the third quadrant.

25. The SOC of claim 24 , wherein the fourth quadrant is separated from the second quadrant by a row decoder, wherein the second quadrant and the fourth quadrant are symmetrical about a vertical axis bisecting the row decoder.

26. A system on chip (SOC) comprising:
a memory circuit having a plurality of quadrants arranged

Assignees

• Qualcomm Inc

Inventors

• Li David
• Biradar Rahul
• Manakkam Veetil Biju
• Chen Po-Hung
• Paul Ayan
• Son Sung
• Kushwaha Shivendra
• Chekkera Ravindra Reddy
• Yang Derek

Classifications

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C8/10

  Decoders · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title