Multi-protocol IO infrastructure for a flexible storage platform

US11907150B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11907150-B2
Application numberUS-202117316385-A
CountryUS
Kind codeB2
Filing dateMay 10, 2021
Priority dateMay 8, 2015
Publication dateFeb 20, 2024
Grant dateFeb 20, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.

First claim

Opening claim text (preview).

What is claimed is: 1. A system, comprising: a storage board; a first storage circuit in communication with the storage board, the first storage circuit configured to support a first storage interface for communicating with a first storage device; and a second storage circuit in communication with the storage board, the second storage circuit configured to support a second storage interface for communicating with a second storage device, wherein the first storage interface is a multi-protocol interface that is different from the second storage interface, and wherein at least one of the first storage circuit or the second storage circuit is configured to: determine, according to a physical connector of the first storage device or the second storage device, a storage protocol used by the first storage device or the second storage device that is different from a storage protocol used by a host interface; and modify a communication, received according to the storage protocol used by the host interface, based on the different storage protocol used by the first storage device or the second storage device. 2. The system of claim 1 , wherein the first storage interface comprises at least one of a Serial Advanced Technology Attachment (SATA) interface or a Serial Attached SCSI (SAS) interface, and the second storage interface comprises a Non Volatile Memory Express (NVMe) interface. 3. The system of claim 1 , wherein the multi-protocol interface is compatible with at least two from among SATA, SAS, or NVMe over Peripheral Component Interconnect Express (PCIe). 4. The system of claim 1 , wherein the multi-protocol interface is compatible with the first storage interface and a third storage interface that is different from the first storage interface. 5. The system of claim 4 , wherein the first storage interface is a SATA interface and the third storage interface is a SAS interface. 6. The system of claim 1 , wherein the first storage circuit comprises a first routing circuit configured to route data access requests to the first storage device. 7. The system of claim 6 , wherein the first routing circuit comprises at least one of a router, a switch, an expander, or a hub. 8. The system of claim 6 , wherein the first storage circuit further comprises a host bus adapter configured to translate between a protocol of a host bus and a protocol of the first storage device. 9. The system of claim 6 , wherein the first storage circuit further comprises a second routing circuit configured to route data access requests to a third storage device configured with a protocol different from that of the first storage device. 10. The system of claim 1 , wherein the storage board comprises a multi-protocol storage interface connector connected to the first storage circuit, and configured to mechanically connect to the first storage device and a third storage device configured with a protocol different from that of the first storage device. 11. A storage adapter circuit, comprising: a first storage circuit in communication with a storage board, the first storage circuit configured to support a first storage interface for communicating with a first storage device; and a second storage circuit in communication with the storage board, the second storage circuit configured to support a second storage interface for communicating with a second storage device, wherein the first storage interface is a multi-protocol interface that is different from the second storage interface, and wherein at least one of the first storage circuit or the second storage circuit is configured to: determine, according to a physical connector of the first storage device or the second storage device, a storage protocol used by the first storage device or the second storage device that is different from a storage protocol used by a host interface; and modify a communication, received according to the storage protocol used by the host interface, based on the different protocol used by the first storage device or the second storage device. 12. The circuit of claim 11 , wherein the first storage interface comprises at least one of a Serial Advanced Technology Attachment (SATA) interface or a Serial Attached SCSI (SAS) interface, and the second storage interface comprises a Non Volatile Memory Express (NVMe) interface. 13. The circuit of claim 11 , wherein the multi-protocol interface is compatible with at least two from among SATA, SAS, or NVMe over Peripheral Component Interconnect Express (PCIe). 14. The circuit of claim 11 , wherein the multi-protocol interface is compatible with the first storage interface and a third storage interface that is different from the first storage interface. 15. The circuit of claim 14 , wherein the first storage interface is a SATA interface and the third storage interface is a SAS interface. 16. The circuit of claim 1 , wherein the first storage circuit comprises a first routing circuit configured to route data access requests to the first storage device. 17. The circuit of claim 16 , wherein the first routing circuit comprises at least one of a router, a switch, an expander, or a hub. 18. The circuit of claim 16 , wherein the first storage circuit further comprises a host bus adapter configured to translate between a protocol of a host bus and a protocol of the first storage device. 19. The circuit of claim 16 , wherein the first storage circuit further comprises a second routing circuit configured to route data access requests to a third storage device configured with a protocol different from that of the first storage device. 20. The circuit of claim 11 , wherein the first storage circuit is configured to communicate with the first storage device and a third storage device configured with a protocol different from that of the first storage device through a multi-protocol storage interface connector of the storage board configured to mechanically connect to the first storage device and the third storage device.

Assignees

Inventors

Classifications

  • G06F13/385Primary

    for adaptation of a particular data processing system to different peripheral devices · CPC title

  • using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

  • on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

  • Details of memory controller · CPC title

  • G06F13/387Primary

    for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title

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What does patent US11907150B2 cover?
A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit ma…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F13/385. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 20 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 11 related publications on this page (citations in our corpus or others sharing the same primary CPC).