Disaggregated memory appliance

Patent metadata

Field	Value
Publication number	US-2016124872-A1
Application number	US-201514867988-A
Country	US
Kind code	A1
Filing date	Sep 28, 2015
Priority date	Dec 12, 2013
Publication date	May 5, 2016
Grant date	—

Abstract

Exemplary embodiments provide a disaggregated memory appliance, comprising: a plurality of leaf memory switches that manage one or more memory channels of one or more of leaf memory modules; a low-latency memory switch that arbitrarily connects one or more external processors to the plurality of leaf memory modules over a host link; and a low-latency routing protocol used by both the low-latency memory switch and the leaf memory switches that encapsulates memory technology specific semantics by use of tags that uniquely identify specific types of memory technology used in the memory appliance during provisioning, monitoring and operation.

First claim

We claim:

1 . A memory appliance, comprising:
a plurality of leaf memory switches that each manage one or more memory channels of one or more of leaf memory modules; and a low-latency memory switch that arbitrarily connects one or more external processors to the plurality of leaf memory modules over a host link; and a low-latency routing protocol used by both the low-latency memory switch and the leaf memory switches that encapsulates memory technology specific semantics by use of tags that uniquely identify specific types of memory technology used in the memory appliance during provisioning, monitoring and operation.

2 . The memory appliance of claim 1 , further comprising: a plurality of leaf links that connect the low-latency memory switch to the plurality of leaf memory switches.

3 . The memory appliance of claim 2 , further comprising a management processor that accepts and processes requests from one or more external processors for access, management, maintenance, configuration and provisioning of the leaf memory modules within the memory appliance; and configures the leaf memory modules and leaf memory switches to satisfy requests for memory.

4 . The memory appliance of claim 3 , wherein the management processor discovers the specific types of memory technology used in the memory appliance and stores in a configuration database the tags for each of the discovered types of memory technology.

5 . The memory appliance of claim 4 , wherein the tags are used to identify context for commands and transactions received in the request from the one or more external processors during operation of the memory appliance.

6 . The memory appliance of claim 3 , wherein the management processor is implemented as part of a compute complex.

7 . The memory appliance of claim 3 , wherein the management processor is implemented in at least a portion of the leaf memory switches.

8 . The memory appliance of claim 1 , wherein the memory appliance uses wormhole switching in which endpoints use target routing data supplied during a memory provisioning process to effect low-latency switching of memory data flits and metadata.

9 . The memory appliance of claim 1 , wherein different types of memory technology are used across multiple memory appliances.

10 . A method for providing a disaggregated memory appliance, comprising:
coupling a low-latency memory switch to a host link over which the low-latency memory switch receives requests and traffic from one or more external processors; using a plurality of leaf links to connect the low-latency memory switch to a plurality of leaf memory switches that are connected to, and manage, one or more memory channels of one or more of leaf memory modules; and using a low-latency routing protocol by both the low-latency memory switch and the leaf memory switches that encapsulates memory technology specific semantics by use of tags that uniquely identify specific types of memory technology used in the memory appliance during provisioning, monitoring and operation.

11 . The method of claim 10 , further comprising:
accepting and processing, by a management processor, the requests from the one or more external processors for access, management, maintenance, configuration and provisioning of the leaf memory modules within the memory appliance; and configuring the leaf memory modules and leaf memory switches to satisfy requests for memory.

12 . The method 11 , further comprising:
discovering, by the management processor, specific types of memory technology used in the memory appliance and storing in a configuration database the tags for each of the discovered types of memory technology.

13 . The method of claim 12 , further comprising:
using the tags to identify context for commands and transactions received in the request from the one or more external processors during operation of the memory appliance.

14 . The method of claim 11 , wherein the management processor is implemented as part of a compute complex.

15 . The method of claim 11 , wherein the management processor is implemented in at least a portion of the leaf memory switches.

16 . The method of claim 10 , further comprising:
using, by the memory appliance, wormhole switching in which endpoints use target routing data supplied during a memory provisioning process to effect low-latency switching of memory data flits and metadata.

17 . The method of claim 16 , wherein different types of memory technology are used across multiple memory appliances.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shrader Steven L
• Rogers Harry R
• Brennan Robert
• Shaeffer Ian P

Classifications

• G06F13/161 Primary

  with latency improvement · CPC title

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title