Memory device

Patent metadata

Field	Value
Publication number	US-11895840-B2
Application number	US-202217895182-A
Country	US
Kind code	B2
Filing date	Aug 25, 2022
Priority date	Jan 17, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.

First claim

What is claimed is:

1. A memory device comprising:
a lower structure; and
a plurality of upper structures stacked on the lower structure,
wherein the lower structure comprises a peripheral circuit and an upper bonding pad connected to the peripheral circuit and disposed on a top surface of the lower structure,
each of the plurality of upper structures has a bottom surface, and each of the plurality of upper structures comprises a stacked structure including a plurality of gate layers stacked in a vertical direction, a plurality of channel structures each passing through the stacked structure in the vertical direction, a bit line disposed under the stacked structure and connected to the plurality of channel structures, a through via passing through the stacked structure in the vertical direction, and a lower bonding pad disposed on the bottom surface and connected to the through via,
each of upper structures, other than an uppermost upper structure, of the plurality of upper structures further comprises a top surface and an upper bonding pad disposed on the top surface and connected to the through via,
the bit line of each of the plurality of upper structures comprises a first portion extending in a horizontal direction orthogonal to the vertical direction, a second portion extending in the horizontal direction, and a gap separating the first portion of the bit line from the second portion in the horizontal direction,
in a plan view, the through via of each of the plurality of upper structures overlaps the gap of the bit line,
a lowermost upper structure of the plurality of upper structures is stacked on the lower structure in the vertical direction so that the lower bonding pad of the lowermost upper structure contacts the upper bonding pad of the lower structure,
the plurality of upper structures comprise a first upper structure and a second upper structure stacked in the vertical direction, and
the lower bonding pad of the second upper structure contacts the upper bonding pad of the first upper structure,
wherein the first portion and the second portion of the bit line of at least one upper structure of the plurality of upper structures are not connected to the lower bonding pad of the at least one upper structure,
wherein the at least one upper structure comprises a first lower line connecting the lower bonding pad of the at least one upper structure to the through via of the at least one upper structure, and a second lower line connecting the first portion of the bit line of the at least one upper structure to the second portion of the bit line of the at least one upper structure and being disconnected from the lower bonding pad of the at least one upper structure, and
wherein a bottom surface of the first lower line of the at least one upper structure is disposed on a same plane as a bottom surface of the second lower line of the at least one upper structure.

2. The memory device of claim 1 , wherein the lower structure comprises a second stacked structure including a plurality of second gate layers stacked on the peripheral circuit in the vertical direction, a plurality of second channel structures each passing through the second stacked structure in the vertical direction, a second bit line disposed on the second stacked structure and connected to the plurality of second channel structures, and a second through via passing through the second stacked structure and connecting the upper bonding pad of the lower structure to the peripheral circuit,
the second bit line of the lower structure comprises a first portion extending in the horizontal direction, a second portion extending in the horizontal direction, and a gap separating the first portion of the second bit line of the lower structure from the second portion of the second bit line in the horizontal direction, and
in a plan view, the second through via of the lower structure overlaps the gap of the second bit line of the lower structure.

3. The memory device of claim 2 , wherein the first portion and the second portion of the second bit line of the lower structure are not connected to the upper bonding pad of the lower structure.

4. The memory device of claim 3 , wherein the lower structure further comprises an upper connection pad connecting the first portion of the second bit line of the lower structure to the second portion of the second bit line.

5. The memory device of claim 4 , wherein a top surface of the upper connection pad of the lower structure is disposed on a same plane as a top surface of the upper bonding pad of the lower structure.

6. The memory device of claim 4 , wherein the lower structure further comprises a first via connecting the upper bonding pad of the lower structure to the second through via, a second via connecting the upper connection pad of the lower structure to the first portion of the second bit line, and a third via connecting the upper connection pad of the lower structure to the second portion of the second bit line.

7. The memory device of claim 3 , wherein the lower structure further comprises a first upper line connecting the upper bonding pad of the lower structure to the second through via, and a second upper line connecting the first portion of the second bit line of the lower structure to the second portion of the second bit line and being disconnected from the upper bonding pad of the lower structure.

8. The memory device of claim 7 , wherein a top surface of the first upper line of the lower structure is disposed on a same plane as a top surface of the second upper line of the lower structure.

9. The memory device of claim 2 , wherein the first portion and the second portion of the second bit line of the lower structure are connected to the upper bonding pad of the lower structure.

10. The memory device of claim 9 , wherein the lower structure further comprises a first via connecting the upper bonding pad of the lower structure to the second through via, a second via connecting the upper bonding pad of the lower structure to the first portion of the second bit line, and a third via connecting the upper bonding pad of the lower structure to the second portion of the second bit line.

11. The memory device of claim 9 , wherein the lower upper structure further comprises a first upper line connecting the upper bonding pad of the lower structure to the second through via of the lower structure and the first portion and the second portion of the second bit line.

12. A memory device comprising:
a first structure; and
a second structure stacked on the first structure,
wherein the first structure comprises a peripheral circuit, a first upper bonding pad connected to the peripheral circuit, and a second upper bonding pad connected to the peripheral circuit,
the second structure comprises a first lower bonding pad connected to the first upper bonding pad of the first structure, a first through via connected to the first lower bonding pad of the second structure, a third upper bonding pad connected to the first through via of the second structure, a second lower bonding pad connected to the second upper bonding pad of the first structure, a first bit line connected to the second lower bonding pad of the second structure, and a memory cell array connected to the first bit line of the second structure,
the first bit line of the second structure comprises a first portion, a second portion, and a first gap between the first portion of the first bit line of the second structure and the second portion of the first bit line of the second structure, and
the first lower bonding pad of the second structure is not connected to the first portion and the second portion of the first bit l

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Woosung
• Lee Byungjin
• Kang Bumkyu
• Lim Joonsung

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W72/922

  Bond pads being integral with underlying chip-level interconnections · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title