Memory device having a plurality of first conductive pillars penetrating through a stacked film

Patent metadata

Field	Value
Publication number	US-10319730-B2
Application number	US-201815927318-A
Country	US
Kind code	B2
Filing date	Mar 21, 2018
Priority date	Sep 22, 2017
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A memory device according to an embodiment includes: a stacked film having a plurality of semiconductor films, and a plurality of insulating films each provided between the semiconductor films; a first electrode provided above the stacked film; a second electrode provided above the stacked film; a plurality of first conductive pillars penetrating through the stacked film and having one end electrically connected to the first electrode and another end not connected and positioned below the stacked film; a plurality of memory cells each provided between each of the first conductive pillars and each of the semiconductor films; a plurality of second conductive pillars electrically connected to each of the semiconductor films and the second electrode; a peripheral circuit board provided above the first electrode and the second electrode; a third electrode provided between the first electrode and the peripheral circuit board, the third electrode electrically connected to the first electrode; a fourth electrode provided between the second electrode and the peripheral circuit board, the fourth electrode electrically connected to the second electrode; and a transistor electrically connected to the third electrode or the fourth electrode, the transistor provided in the peripheral circuit board.

First claim

What is claimed is:

1. A memory device comprising:
a stacked film having a plurality of semiconductor films, and a plurality of insulating films each provided between the semiconductor films;
a first electrode provided above the stacked film;
a second electrode provided above the stacked film;
a plurality of first conductive pillars penetrating through the stacked film, each of the first conductive pillars having one end electrically connected to the first electrode and another end not connected to the other first conductive pillars, the another end positioned below the stacked film;
a plurality of memory cells each provided between each of the first conductive pillars and each of the semiconductor films;
a plurality of second conductive pillars electrically connected to each of the semiconductor films and the second electrode;
a peripheral circuit board provided above the first electrode and the second electrode;
a third electrode provided between the first electrode and the peripheral circuit board, the third electrode electrically connected to the first electrode;
a fourth electrode provided between the second electrode and the peripheral circuit board, the fourth electrode electrically connected to the second electrode; and
a transistor electrically connected to the third electrode or the fourth electrode, the transistor provided in the peripheral circuit board.

2. The memory device according to claim 1 , wherein
the first conductive pillars are a plurality of gate electrodes.

3. The memory device according to claim 1 , wherein
an area of one semiconductor film among the semiconductor films is smaller than an area of the other semiconductor films provided below the one semiconductor film.

4. The memory device according to claim 1 , further comprising:
a first memory cell insulator provided around the first electrode and the second electrode; and
a peripheral circuit insulator provided around the third electrode and the fourth electrode, wherein
the first electrode, the second electrode, the third electrode, and the fourth electrode contain copper.

5. The memory device according to claim 4 , wherein
the first memory cell insulator and the peripheral circuit insulator contain silicon oxide, silicon oxynitride, or carbon-added silicon oxide.

6. The memory device according to claim 4 , further comprising:
a second memory cell insulator, wherein
the first memory cell insulator is provided between the second memory cell insulator and the peripheral circuit insulator.

7. The memory device according to claim 6 , wherein
the second memory cell insulator contains tantalum oxide or aluminum oxide.

8. The memory device according to claim 1 , wherein
the transistor includes a source portion and a drain portion, and
the source portion and the drain portion each contains metal silicide.

9. The memory device according to claim 8 , wherein
the metal silicide includes titanium silicide, aluminum silicide, nickel silicide, cobalt silicide, tantalum silicide, tungsten silicide, or hafnium silicide.

10. The memory device according to claim 1 , wherein
the transistor includes a channel portion containing a crystalline semiconductor.

Assignees

• Toshiba Memory Corp

Inventors

• Matsuo Kouji

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/5226

  Electricity · mapped topic

• H01L2224/08146

  Electricity · mapped topic