Two-wire communication systems and applications

Patent metadata

Field	Value
Publication number	US-11874791-B2
Application number	US-202217589715-A
Country	US
Kind code	B2
Filing date	Jan 31, 2022
Priority date	Oct 5, 2011
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

First claim

What is claimed is:

1. Vehicle equipment with low-latency noise cancellation capability, comprising:
an accelerometer; and
a node transceiver, including:
upstream transceiver circuitry to receive, from upstream equipment, a first signal over two upstream wires of a two-wire bus and to provide, to the upstream equipment, a second signal over the two upstream wires of the two-wire bus;
clock circuitry to generate a clock signal at the node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal;
power circuitry to receive, from the upstream equipment, a voltage bias between the two upstream wires of the two-wire bus; and
interface circuitry to communicate with the accelerometer.

2. The vehicle equipment of claim 1 , wherein the accelerometer is communicatively coupled to the node transceiver via at least one of an Inter-Integrated Circuit Sound (I2S) interface, a pulse code modulated (PDM) interface, a time division multiplexed (TDM) interface, or an Inter-Integrated Circuit (I2C) interface.

3. The vehicle equipment of claim 1 , further comprising:
processing circuitry communicatively coupled with the node transceiver, wherein the accelerometer is to provide acceleration data to the processing circuitry, and wherein the processing circuitry is to generate a noise cancellation signal based at least in part on the acceleration data from the accelerometer.

4. The vehicle equipment of claim 3 , further comprising:
a microphone communicatively coupled with the processing circuitry, wherein the microphone is to provide microphone data to the processing circuitry, and wherein the processing circuitry is to generate the noise cancellation signal based at least in part on data from the microphone.

5. The vehicle equipment of claim 4 , wherein the microphone is communicatively coupled with the processing circuitry via the two-wire bus.

6. The vehicle equipment of claim 3 , further comprising:
a speaker communicatively coupled with the processing circuitry, the speaker is to receive the noise cancellation signal and output noise cancellation audio.

7. The vehicle equipment of claim 6 , wherein the speaker is communicatively coupled with the processing circuitry via the two-wire bus.

8. The vehicle equipment of claim 3 , wherein the noise cancellation signal is to cancel, at least in part, road noise.

9. The vehicle equipment of claim 3 , wherein the noise cancellation signal is a multichannel noise cancellation signal.

10. Vehicle equipment with low-latency noise cancellation capability, comprising:
an electromechanical sensor; and
a node transceiver including:
upstream transceiver circuitry to receive, from upstream equipment, a first signal over two upstream wires of a two-wire bus and to provide, to the upstream equipment, a second signal over the two upstream wires of the two-wire bus;
clock circuitry to generate a clock signal at the node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal;
power circuitry to receive, from the upstream equipment, a voltage bias between the two upstream wires of the two-wire bus; and
interface circuitry to communicate with the electromechanical sensor.

11. The vehicle equipment of claim 10 , wherein the electromechanical sensor is communicatively coupled to the node transceiver via at least one of an Inter-Integrated Circuit Sound (I2S) interface, a pulse code modulated (PDM) interface, a time division multiplexed (TMD) interface, or an Inter-Integrated Circuit (I2C) interface.

12. The vehicle equipment of claim 10 , further comprising:
processing circuitry to generate a noise cancellation signal based at least in part on data from the electromechanical sensor, the processing circuitry being communicatively coupled with the node transceiver.

13. The vehicle equipment of claim 12 , further comprising:
a speaker to receive the noise cancellation signal and output noise cancellation audio, the speaker being communicatively coupled with the processing circuitry.

14. The vehicle equipment of claim 12 , further comprising:
a microphone communicatively coupled with the processing circuitry, the microphone is to provide microphone data to the processing circuitry, wherein the processing circuitry is to generate the noise cancellation signal based at least in part on data from the microphone.

15. The vehicle equipment of claim 14 , wherein the microphone is communicatively coupled with the processing circuitry via the two-wire bus.

16. The vehicle equipment of claim 12 , wherein the noise cancellation signal is to cancel, at least in part, road noise.

17. The vehicle equipment of claim 10 , wherein the electromechanical sensor is to detect chassis vibration.

18. Vehicle equipment with road noise cancellation capability, comprising:
a peripheral device; and
a node transceiver including:
upstream transceiver circuitry to receive a first signal, from upstream equipment, over two upstream wires of a two-wire bus and to provide, to the upstream equipment, a second signal over the two upstream wires of the two-wire bus;
clock circuitry to generate a clock signal at the node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal;
power circuitry to receive a voltage bias between the two upstream wires of the two-wire bus from the upstream equipment; and
interface circuitry to communicate with the peripheral device.

19. The vehicle equipment of claim 18 , further comprising:
a second peripheral device; and
a second node transceiver including:
downstream transceiver circuitry to receive, from downstream equipment, a third signal over two downstream wires of the two-wire bus and to provide, to the downstream equipment, a fourth signal over the two downstream wires of the two-wire bus;
clock circuitry to generate a second clock signal at the second node transceiver based on a preamble of a synchronization control frame in the third signal, wherein timing of receipt and provision of signals over the two-wire bus by the second node transceiver is based on the second clock signal;
power circuitry to provide, to the downstream equipment, a voltage bias between the two downstream wires of the two-wire bus; and
interface circuitry to communicate with the second peripheral device.

20. The vehicle equipment of claim 19 , wherein the peripheral device and the second peripheral device are disposed at opposite sides of a vehicle cabin.

21. The vehicle equipment of claim 19 , wherein the peripheral device comprises at least one of a microphone, a speaker, an accelerometer, a gyroscope, or an ultrasonics sensor, a digital signal processor (DSP), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an analog to digital converter (ADC), a digital to analog converter (DAC), a codec, a microphone array, an audio amplifier, a temperature sensor, a humidity sensor, a gas sensor, a display device, a user interface component, a camera, or a memory device, and
wherein the second peripheral device comprises at least one of a second microphone, a second speaker,

Assignees

• Analog Devices Inc

Inventors

• Kessler Martin
• Chavez Miguel A
• Lahr Lewis F
• Hooper William
• Adams Robert
• Sealey Peter

Classifications

• G06F13/426 Primary

  using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus · CPC title

• G05B19/0421

  Multiprocessor system · CPC title

• G05B19/0423 Primary

  Input/output · CPC title

• G05B19/4185

  characterised by the network communication · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title