Two-wire communication systems and applications

Patent metadata

Field	Value
Publication number	US-10311010-B2
Application number	US-201514884900-A
Country	US
Kind code	B2
Filing date	Oct 16, 2015
Priority date	Oct 5, 2011
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

First claim

What is claimed is:

1. A slave device for low-latency communication, comprising:
a slave node transceiver, including:
upstream transceiver circuitry to receive a first signal transmitted over two upstream wires of a two-wire bus from an upstream device and to provide a second signal over the two upstream wires of the two-wire bus to the upstream device;
clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the slave node transceiver is based on the clock signal; and
power circuitry to receive a voltage bias between the two upstream wires of the two-wire bus from the upstream device.

2. The slave device of claim 1 , wherein the slave node transceiver further includes downstream transceiver circuitry to provide a third signal downstream over two downstream wires of the two-wire bus toward a downstream device and to receive a fourth signal over the two downstream wires of the two-wire bus from the downstream device, the synchronization control frame is associated with downstream data in a superframe of the first signal, the downstream data includes multiple data slots, and data for a single peripheral device in communication with the slave node transceiver occupies two or more of the multiple data slots.

3. The slave device of claim 1 , wherein the slave node transceiver further includes downstream transceiver circuitry to provide a third signal downstream over two downstream wires of the two-wire bus toward a downstream device and to receive a fourth signal over the two downstream wires of the two-wire bus from the downstream device, the second signal includes a synchronization response frame, the synchronization response frame is associated with upstream data in a superframe of the second signal, the upstream data includes multiple data slots, and data originating at a single peripheral device in communication with the slave node transceiver occupies two or more of the multiple data slots.

4. The slave device of claim 1 , wherein the power circuitry is further to provide energy from the voltage bias to an energy storage device coupled to the slave node transceiver.

5. The slave device of claim 1 , further comprising peripheral device communication circuitry to communicate with a microphone and a conferencing user interface element, wherein a user actuates the conferencing user interface element when the user wishes to provide audio from the microphone to another device coupled to the two-wire bus, and wherein the second signal includes data originating at the microphone when the conferencing user interface element is actuated.

6. The slave device of claim 1 , wherein the upstream device is coupled to a wireless transceiver, the wireless transceiver is to receive voice calls, and the upstream transceiver circuitry is to receive data representative of the voice calls in the first signal.

7. The slave device of claim 1 , further comprising peripheral device communication circuitry in communication with an antenna coupled to a vehicle, wherein the peripheral device communication circuitry communicates with the antenna via a wired connection.

8. The slave device of claim 7 , wherein the upstream device is a master device located at a head unit of the vehicle.

9. The slave device of claim 1 , further comprising peripheral device communication circuitry in communication with a sensor or an actuator at a joint of a robotic limb.

10. The slave device of claim 1 , further comprising a receive mailbox and a transmit mailbox, wherein the slave node transceiver is to generate an interrupt for transmission to a host device coupled to a master node of the two-wire bus when data is provided to the transmit mailbox.

11. The slave device of claim 1 , further comprising:
a first connector to couple to a microphone;
a second connector to couple to an audio receiving device; and
a conductor to transmit data between the first connector and the second connector;
wherein the slave node transceiver further includes peripheral device communication circuitry coupled to the conductor to receive the data transmitted between the first connector and the second connector, the data is included in the second signal, and the first connector, the second connector, the conductor, and the slave node transceiver are included in a microphone cable.

12. The slave device of claim 11 , further comprising an analog to digital converter (ADC) to convert an analog microphone input received at the first connector to a digital signal, wherein the data transmitted between the first connector of the second connector includes the digital signal.

13. The slave device of claim 12 , wherein the second connector is to provide the second signal and the analog microphone input to the audio receiving device.

14. The slave device of claim 12 , further comprising a digital to analog converter (DAC) to convert the digital signal to an analog signal.

15. A master node transceiver for low-latency communication, comprising:
an Inter-Integrated Circuit Sound (I2S) receiver to receive an I2S signal from a host device, wherein the I2S signal provides clock information;
clock circuitry to generate a clock signal based on the clock information; and
downstream transceiver circuitry to provide a first signal downstream over two downstream wires of a two-wire bus toward a downstream device and to receive a second signal over the two downstream wires of the two-wire bus from the downstream device, wherein a preamble of a synchronization control frame of the first signal is based on the clock signal, and the downstream device generates its own clock signal based on the preamble;
wherein the master node transceiver is further to provide a voltage bias between the two downstream wires of the two-wire bus.

16. The master node transceiver of claim 15 , wherein:
the first signal includes a first synchronization control frame and associated first downstream data and a second synchronization control frame and associated second downstream data;
the first downstream data includes a data slot having a particular index and including data for a first peripheral device coupled to the downstream device; and
the second downstream data includes a data slot having the particular index and including data for a second peripheral device, different from the first peripheral device, coupled to the downstream device.

17. The master node transceiver of claim 15 , wherein the downstream device is coupled to a wireless transceiver, the wireless transceiver is to receive voice calls, and the downstream transceiver circuitry is to receive data representative of the voice calls in the second signal.

18. A host device, comprising:
Inter-Integrated Circuit Sound (I2S) transceiver circuitry to provide an I2S signal to a master node transceiver, wherein the master node transceiver is a master of a two-wire bus, the I2S signal provides clock information, the master node transceiver is to generate a clock signal based on the clock information, the master node transceiver is to provide a first signal downstream over two downstream wires of the two-wire bus toward a downstream device, a preamble of a synchronization control frame of the first signal is based on the clock signal, the downstream device is to generate its own clock signal based on the preamble, and the master node transceiver is further to provide a voltage bias between the two downstream wires of the two-wire bus;
Inter-In

Assignees

• Analog Devices Inc

Inventors

• Kessler Martin
• Chavez Miguel
• Lahr Lewis F
• Hooper William
• Adams Robert
• Sealey Peter

Classifications

• G05B19/4185

  characterised by the network communication · CPC title

• H04B3/548

  the power on the line being DC (arrangements for feeding power H04L12/10; extracting feeding power from signals H04L25/02) · CPC title

• H04B2203/547

  via DC power distribution · CPC title

• Y02D10/151

  Cross-Sectional Technologies · mapped topic

• H04L12/4035

  in which slots of a TDMA packet structure are assigned based on a contention resolution carried out at a master unit (TDM/TDMA multiplex systems per se H04J3/1694; hybrid switching systems H04L12/64) · CPC title