Two-wire communication systems and applications

US11238004B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11238004-B2
Application numberUS-202016859611-A
CountryUS
Kind codeB2
Filing dateApr 27, 2020
Priority dateOct 5, 2011
Publication dateFeb 1, 2022
Grant dateFeb 1, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

First claim

Opening claim text (preview).

What is claimed is: 1. Vehicle equipment with low-latency noise cancellation capability, comprising: a microphone; and a node transceiver, including: upstream transceiver circuitry to receive a first signal transmitted over two upstream wires of a two-wire bus from an upstream equipment and to provide a second signal over the two upstream wires of the two-wire bus to the upstream equipment; clock circuitry to generate a clock signal at the node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal; power circuitry to receive a voltage bias between the two upstream wires of the two-wire bus from the upstream equipment; and interface circuitry to communicate with the microphone. 2. The vehicle equipment of claim 1 , wherein the microphone is communicatively coupled to the node transceiver via an Inter-Integrated Circuit Sound (I2S) interface or an Inter-Integrated Circuit (I2C) interface. 3. The vehicle equipment of claim 1 , further comprising: processing circuitry, communicatively coupled with the node transceiver, to generate a noise cancellation signal based at least in part on data from the microphone. 4. The vehicle equipment of claim 3 , further comprising: an accelerometer, communicatively coupled with the processing circuitry, to provide acceleration data to the processing circuitry, wherein the processing circuitry is to generate the noise cancellation signal based at least in part on data from the accelerometer. 5. The vehicle equipment of claim 4 , wherein the accelerometer is communicatively coupled with the processing circuitry via the two-wire bus. 6. The vehicle equipment of claim 3 , further comprising: a speaker, communicatively coupled with the processing circuitry, to receive the noise cancellation signal and output noise cancellation audio. 7. The vehicle equipment of claim 6 , wherein the speaker is communicatively coupled with the processing circuitry via the two-wire bus. 8. The vehicle equipment of claim 3 , wherein the noise cancellation signal is to cancel, at least in part, road noise. 9. The vehicle equipment of claim 3 , wherein the noise cancellation signal is a multichannel noise cancellation signal. 10. Vehicle equipment with low-latency noise cancellation capability, comprising: a speaker; and a node transceiver, including: upstream transceiver circuitry to receive a first signal transmitted over two upstream wires of a two-wire bus from an upstream equipment and to provide a second signal over the two upstream wires of the two-wire bus to the upstream equipment; clock circuitry to generate a clock signal at the node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal; power circuitry to receive a voltage bias between the two upstream wires of the two-wire bus from the upstream equipment; and interface circuitry to communicate with the speaker. 11. The vehicle equipment of claim 10 , wherein the speaker is communicatively coupled to the node transceiver via an Inter-Integrated Circuit Sound (I2S) interface or an Inter-Integrated Circuit (I2C) interface. 12. The vehicle equipment of claim 10 , further comprising: processing circuitry, communicatively coupled with the node transceiver, to generate a noise cancellation signal, and the speaker is to output noise cancellation audio based at least in part on the noise cancellation signal. 13. The vehicle equipment of claim 12 , further comprising: an accelerometer, communicatively coupled with the processing circuitry, to provide acceleration data to the processing circuitry, wherein the processing circuitry is to generate the noise cancellation signal based at least in part on data from the accelerometer. 14. The vehicle equipment of claim 13 , wherein the accelerometer is to detect chassis vibration. 15. The vehicle equipment of claim 12 , further comprising: a microphone, communicatively coupled with the processing circuitry, to provide microphone data to the processing circuitry, wherein the processing circuitry is to generate the noise cancellation signal based at least in part on data from the microphone. 16. The vehicle equipment of claim 15 , wherein the microphone is communicatively coupled with the processing circuitry via the two-wire bus. 17. The vehicle equipment of claim 12 , wherein the noise cancellation signal is to cancel, at least in part, road noise. 18. Vehicle equipment with road noise cancellation capability, comprising: a microphone, wherein the microphone is to detect road noise; and a node transceiver, including: upstream transceiver circuitry to receive a first signal transmitted over two upstream wires of a two-wire bus from an upstream equipment and to provide a second signal over the two upstream wires of the two-wire bus to the upstream equipment; clock circuitry to generate a clock signal at the node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal; power circuitry to receive a voltage bias between the two upstream wires of the two-wire bus from the upstream equipment; and interface circuitry to communicate with the microphone. 19. The vehicle equipment of claim 18 , wherein the microphone is a first microphone, the node transceiver is a first node transceiver, the clock signal is a first clock signal, and the vehicle equipment further includes: a second microphone, wherein the second microphone is to detect road noise; and a second node transceiver, including: downstream transceiver circuitry to receive a third signal transmitted over two downstream wires of the two-wire bus from a downstream equipment and to provide a fourth signal over the two downstream wires of the two-wire bus to the downstream equipment; clock circuitry to generate a second clock signal at the second node transceiver based on a preamble of a synchronization control frame in the third signal, wherein timing of the receipt and provision of signals over the two-wire bus by the second node transceiver is based on the second clock signal; power circuitry to provide a voltage bias between the two downstream wires of the two-wire bus to the downstream equipment; and interface circuitry to communicate with the second microphone. 20. The vehicle equipment of claim 19 , wherein the first microphone and the second microphone are at opposite sides of a vehicle cabin.

Assignees

Inventors

Classifications

  • Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

  • G06F13/426Primary

    using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus · CPC title

  • using an embedded synchronisation · CPC title

  • for combining the signals of two or more microphones (specially adapted for hearing aids H04R25/407) · CPC title

  • Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

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Frequently asked questions

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What does patent US11238004B2 cover?
Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provi…
Who is the assignee on this patent?
Analog Devices Inc
What technology area does this patent fall under?
Primary CPC classification G06F13/426. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).