Laminated capacitor and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11869929-B2
Application number	US-202117402735-A
Country	US
Kind code	B2
Filing date	Aug 16, 2021
Priority date	Jun 16, 2020
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A laminated capacitor and a method for manufacturing the same are provided. The method includes operations of providing a substrate; forming a first isolation insulation spacer and a plurality of discrete bottom bonding pads on the substrate; forming a sub-capacitor structure on the bottom bonding pads, which comprises a plurality of discrete bottom electrodes, a plurality of discrete top electrodes, and a dielectric medium located between the bottom electrodes and the top electrodes, wherein the plurality of bottom bonding pads are respectively electrically connected with the plurality of bottom electrodes in one-to-one correspondence; and repeatedly performing an operation of forming a connection structure and the sub-capacitor structure for N times on the sub-capacitor structure, such that N connection structures and N+1 sub-capacitor structures are alternately arranged along a direction perpendicular to the substrate, wherein N is an integer greater than or equal to 1.

First claim

The invention claimed is:

1. A method for manufacturing a laminated capacitor, comprising:
providing a substrate;
forming a first isolation insulation spacer and a plurality of discrete bottom bonding pads arranged in the first isolation insulation spacer on the substrate;
forming a first sub-capacitor structure on the first isolation insulation spacer and the bottom bonding pads, which comprises a plurality of discrete bottom electrodes, a plurality of discrete top electrodes, and a dielectric medium located between the bottom electrodes and the top electrodes, wherein the plurality of bottom bonding pads are respectively electrically connected with the plurality of bottom electrodes in one-to-one correspondence; and
performing an operation of sequentially forming a n th connection structure and a n th sub-capacitor structure on the first sub-capacitor structure from n=1 to n=N, wherein N is an integer greater than or equal to 1,
wherein the laminated capacitor finally has N connection structures and N+1 sub-capacitor structures which are alternately arranged along a direction perpendicular to the substrate.

2. The method for manufacturing a laminated capacitor of claim 1 , wherein the connection structures comprises a second isolation insulation spacer, a plurality of discrete bottom electrode connection spacers, and a plurality of discrete top electrode connection spacers;
wherein along the direction perpendicular to the substrate, each bottom electrode connection spacer is electrically connected with two bottom electrodes adjacent thereto, and each top electrode connection spacer is electrically connected with two top electrodes adjacent thereto.

3. The method for manufacturing a laminated capacitor of claim 2 , wherein forming the connection structure on the sub-capacitor structure comprises:
forming the plurality of discrete bottom electrode connection spacers on the sub-capacitor structure;
forming the second isolation insulation spacer between the bottom electrode connection spacers, which has openings respectively exposing the top electrodes; and
forming the top electrode connection spacers in the openings.

4. The method for manufacturing a laminated capacitor of claim 3 , wherein forming the second isolation insulation spacer between the bottom electrode connection spacers, in which the second isolation insulation spacer has the openings respectively exposing the top electrodes comprises:
forming a second isolation insulation spacer layer on a top and a sidewall of each of the bottom electrode connection spacers, and between the bottom electrode connection spacers; and
removing the second isolation insulation spacer layer on the top of each of the bottom electrode connection spacers and between the bottom electrode connection spacers by dry etching to form the openings respectively exposing the top electrodes,
wherein the second isolation insulation spacer layer reserved on the sidewall of each of the bottom electrode connection spacers form the second isolation insulation spacer.

5. The method for manufacturing a laminated capacitor of claim 4 , wherein
a width of the openings is the same as a width of the top electrodes.

6. The method for manufacturing a laminated capacitor of claim 2 , wherein forming the connection structure on the sub-capacitor structure comprises:
forming the plurality of discrete bottom electrode connection spacers on the sub-capacitor structure;
forming the second isolation insulation spacer between the bottom electrode connection spacers, which has openings respectively exposing the top electrodes;
forming third isolation insulation columns respectively in the openings;
forming a sacrificial layer on the bottom electrode connection spacers, the second isolation insulation spacer, and the third isolation insulation columns; and
forming the sub-capacitor structure in the sacrificial layer, and forming the top electrode connection spacers respectively at locations of the third isolation insulation columns, wherein the top electrodes of the sub-capacitor structure and the top electrode connection spacers are integrally formed.

7. The method for manufacturing a laminated capacitor of claim 6 , wherein the third isolation insulation columns are removed by a wet etching process, and the top electrode connection spacers are respectively formed at locations where the third isolation insulation columns had been present.

8. The method for manufacturing a laminated capacitor of claim 1 , further comprising: after repeatedly performing the operation of sequentially forming the n th connection structure and the n th sub-capacitor structure for N times,
forming a top electrode connection structure on the N th sub-capacitor structure, which integrally connects the discrete top electrodes.

9. The method for manufacturing a laminated capacitor according to claim 8 , further comprising: forming a top bonding pad on the top electrode connection structure, wherein the top bonding pad being electrically connected with the top electrode connection structure.

10. A laminated capacitor, comprising:
a substrate;
a first isolation insulation spacer and a plurality of discrete bottom bonding pads arranged in the first isolation insulation spacer on the substrate;
N connection structures and N+1 sub-capacitor structures located on the first isolation insulation spacer and the bottom bonding pads, wherein N is an integer greater than or equal to 1, and the N+1 sub-capacitor structures and the N connection structures are alternately arranged along a direction perpendicular to the substrate;
wherein each of the sub-capacitor structures comprises a plurality of discrete bottom electrodes, a plurality of discrete top electrodes, and a dielectric medium between the bottom electrodes and the top electrodes; and the plurality of bottom bonding pads are respectively electrically connected with the plurality of bottom electrodes of a sub-capacitor structure adjacent to the plurality of bottom bonding pads in one-to-one correspondence.

11. The laminated capacitor of claim 10 , wherein each of the connection structures comprises a second isolation insulation spacer, a plurality of discrete bottom electrode connection spacers, and a plurality of discrete top electrode connection spacers, wherein along the direction perpendicular to the substrate, each of the bottom electrode connection spacers is electrically connected with two bottom electrodes adjacent to the bottom electrode connection spacer, and each of the top electrode connection spacers is electrically connected with two top electrodes adjacent thereto.

12. The laminated capacitor of claim 11 , wherein
each of the bottom electrodes comprises a first columnar body, and multiple layers of first annular side wings connected to a sidewall of the first columnar body, in which each layer of the first annular side wing is discretely arranged; and
each of the top electrodes comprises a second columnar body, and multiple layers of second annular side wings connected to a sidewall of the second columnar body, in which each layer of the second annular side wing is discretely arranged.

13. The laminated capacitor of claim 12 , wherein a width of the top electrode connection spacers is the same as a width of the second columnar bodies.

14. The laminated capacitor of claim 13 , wherein material of the top electrode connection spacers is the same as material of the top electrodes.

15. The laminated capacitor of claim 14 , wherein each top electrode connection spacer and the second columnar body of each top electrode on the top electrode connection

Assignees

• Changxin Memory Tech Inc

Inventors

• Xia Jun
• Bai Shijie

Classifications

• H10D1/716

  having vertical extensions · CPC title

• H10D1/714

  having horizontal extensions · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H01L28/87 Primary

  Electricity · mapped topic

• H01L28/91

  Electricity · mapped topic