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Capacitor and method for fabricating the same
US8993396B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993396-B2 |
| Application number | US-201213596007-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 27, 2012 |
| Priority date | May 8, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating a capacitor, comprising: forming a plurality of cylinder type lower electrodes; forming a first upper electrode inside the cylinder type lower electrodes; forming a second upper electrode outside the cylinder type lower electrodes after the forming of the first upper electrode; and forming a third upper electrode that connects the first upper electrode and the second upper electrode. 2. The method of clai…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D1/042Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8993396B2 cover?
- A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type l…
- Who is the assignee on this patent?
- Park Jong-Kook, Cho Yong-Tae, Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D1/042. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).