Built-in self-test circuits and semiconductor integrated circuits including the same

Patent metadata

Field	Value
Publication number	US-11867757-B2
Application number	US-202117465337-A
Country	US
Kind code	B2
Filing date	Sep 2, 2021
Priority date	Dec 14, 2020
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A semiconductor integrated circuit includes a digital-to-analog converter and a built-in self-test circuit. The digital-to-analog converter performs a normal conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device. The built-in self-test circuit, while the digital-to-analog converter performs the normal conversion operation, performs a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal such that the comparison alarm signal indicates whether the digital-to-analog converter operates normally. Performance and reliability of the digital-to-analog converter and the semiconductor integrated circuit including the digital-to-analog converter may be enhanced by monitoring in real-time abnormality of the digital-to-analog converter using the on-time monitor.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
a digital-to-analog converter configured to perform a conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device;
an analog-to-digital converter configured to generate a digital output signal by converting the analog output signal; and
a built-in self-test circuit configured to, while the digital-to-analog converter performs the conversion operation, perform a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal, the comparison alarm signal indicating whether the digital-to-analog converter operates, the built-in self-test circuit including an on-time monitor comprising:
a delay circuit configured to generate a digital delay signal by delaying the digital input signal based on a digital delay amount of the digital-to-analog converter and an analog delay amount of the analog-to-digital converter, and
a comparison circuit configured to generate the comparison alarm signal by comparing the digital output signal and the digital delay signal.

2. The semiconductor integrated circuit of claim 1 , wherein the comparison circuit is configured to generate the comparison alarm signal having a pass value when a difference value between the digital output signal and the digital delay signal is equal to or smaller than a reference value, and is configured to generate the comparison alarm signal having a fail value when the difference value between the digital output signal and the digital delay signal is greater than the reference value.

3. The semiconductor integrated circuit of claim 1 , further comprising:
a clock divider configured to generate, by dividing an external clock signal, a first clock signal having a first frequency, a second clock signal having a second frequency and a third clock signal having the second frequency, the first clock signal being provided to the digital-to-analog converter, the second clock signal being provided to the analog-to-digital converter, and the third clock signal being provided to the comparison circuit.

4. The semiconductor integrated circuit of claim 3 , wherein the first frequency is equal to the second frequency, a phase difference between the first clock signal and the second clock signal is 90 degrees, and a phase difference between the first clock signal and the third clock signal is zero or 180 degrees.

5. The semiconductor integrated circuit of claim 3 , wherein the first frequency is twice the second frequency, and a phase difference between the second clock signal and the third clock signal is 90 degrees.

6. The semiconductor integrated circuit of claim 3 , wherein the delay circuit includes:
a monitor retiming circuit configured to generate a retimed digital signal by synchronizing the digital input signal with an edge of the second clock signal; and
a delay unit configured to generate the digital delay signal by delaying the retimed digital signal by N times of a clock cycle corresponding to the second frequency where N is a positive integer.

7. The semiconductor integrated circuit of claim 3 , further comprising:
an input retiming circuit configured to generate a retimed digital signal by synchronizing the digital input signal corresponding to the external digital signal with rising edges of the first clock signal,
wherein the clock divider is configured to generate the first clock signal such that the first frequency is half a frequency of the external clock signal and rising edges and falling edges of the first clock signal are synchronized with edges of the external clock signal, and
wherein the external digital signal is provided to the semiconductor integrated circuit such that the external digital signal is synchronized with rising edges of the external clock signal.

8. The semiconductor integrated circuit of claim 1 , wherein the built-in self-test circuit further includes:
a digital test signal generator configured to generate a digital test signal; and
an input multiplexer configured to output the digital input signal by selecting one of the external digital signal and the digital test signal, and
wherein the on-time monitor is further configured to perform a monitor test operation to generate the comparison alarm signal indicating whether the on-time monitor operates based on the digital input signal corresponding to the digital test signal.

9. The semiconductor integrated circuit of claim 8 ,
wherein the monitor test operation includes a pass test operation to determine whether the comparison alarm signal has a pass value when the comparison circuit operates in a first manner and a fail test operation to determine whether the comparison alarm signal has a fail value when the comparison circuit operates in a second manner.

10. The semiconductor integrated circuit of claim 8 , wherein the on-time monitor includes:
a first comparison multiplexer configured to output a first comparison selection signal by selecting one of the digital delay signal and the digital test signal; and
a second comparison multiplexer configured to output a second comparison selection signal by selecting one of the digital delay signal and the digital output signal,
wherein the comparison circuit is configured to generate the comparison alarm signal by comparing the first comparison selection signal and the second comparison selection signal.

11. The semiconductor integrated circuit of claim 10 , wherein, during the real-time monitoring operation, the first comparison multiplexer is configured to output the digital delay signal as the first comparison selection signal, and the second comparison multiplexer is configured to output the digital output signal as the second comparison selection signal.

12. The semiconductor integrated circuit of claim 10 , wherein, during a pass test operation to determine whether the comparison alarm signal has a pass value when the comparison circuit operates in a first manner, the first comparison multiplexer is configured to output the digital delay signal as the first comparison selection signal, and the second comparison multiplexer is configured to output the digital delay signal as the second comparison selection signal.

13. The semiconductor integrated circuit of claim 10 , wherein, during a fail test operation to determine whether the comparison alarm signal has a fail value when the comparison circuit operates in a second manner, the first comparison multiplexer is configured to output the digital test signal as the first comparison selection signal, and the second comparison multiplexer is configured to output the digital delay signal as the second comparison selection signal.

14. The semiconductor integrated circuit of claim 1 , further comprising:
wherein the built-in self-test circuit includes a plurality of on-time monitors that are connected in parallel to the digital-to-analog converter and the analog-to-digital converter,
wherein the built-in self-test circuit is further configured to perform a monitor test operation with respect to each of the plurality of on-time monitors operates, and
wherein the built-in self-test circuit is further configured to perform the real-time monitoring operation using one operating on-time monitor among the plurality of on-time monitors.

15. A semiconductor integrated circuit comprising:
a first input multiplexer configured to o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Heejune
• Park Jinwoo
• Park Younghyo
• Oh Eunhye
• Lee Sungno
• Cho Youngjae
• Choi Michael

Classifications

• G01R31/31725 Primary

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/31724

  Test controller, e.g. BIST state machine (for scan test G01R31/318555) · CPC title

• H03M1/1071

  Measuring or testing · CPC title

• H03M1/108 Primary

  Converters having special provisions for facilitating access for testing purposes · CPC title

• G01R31/3187 Primary

  Built-in tests · CPC title