Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects

Patent metadata

Field	Value
Publication number	US-11854882-B2
Application number	US-202017085882-A
Country	US
Kind code	B2
Filing date	Oct 30, 2020
Priority date	May 27, 2016
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

First claim

What is claimed is:

1. A method of fabricating a back end of line (BEOL) metallization layer for a semiconductor structure, the method comprising:
forming a metal layer above a substrate;
performing a first photobucket process to form one or more conductive vias in the metal layer;
performing a second photobucket process to form one or more cut locations in the metal layer;
performing a third photobucket process to form one or more conductive tabs in the metal layer; and
subtractively etching a plurality of metal lines in the metal layer, the plurality of metal lines coupled to the one or more conductive vias, coupled to the one or more conductive tabs, and having a continuity broken by the one or more cut locations.

2. The method of claim 1 , further comprising forming an inter-layer dielectric (ILD) layer between the plurality of metal lines.

3. The method of claim 2 , further comprising forming dielectric plugs in the one or more cut locations.

4. The method of claim 3 , wherein forming the dielectric plugs comprises forming a same dielectric material as the ILD layer.

5. The method of claim 4 , wherein the dielectric plugs are continuous with the ILD layer.

6. The method of claim 3 , wherein forming the dielectric plugs comprises forming a different dielectric material the ILD layer.

7. The method of claim 1 , wherein the first photobucket process is performed prior to the second photobucket process, and the second photobucket process is performed prior to the third photobucket process.

8. The method of claim 1 , wherein the second photobucket process is performed prior to the first photobucket process, and the first photobucket process is performed prior to the third photobucket process.

9. The method of claim 1 , wherein the third photobucket process is performed prior to the second photobucket process, and the second photobucket process is performed prior to the first photobucket process.

10. The method of claim 1 , wherein the third photobucket process is performed prior to the first photobucket process, and the first photobucket process is performed prior to the second photobucket process.

11. A method of fabricating a back end of line (BEOL) metallization layer for a semiconductor structure, the method comprising:
forming an inter-layer dielectric (ILD) layer disposed above a substrate;
forming a plurality of conductive lines disposed in the ILD layer along a first direction;
forming a conductive tab disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction; and
forming a conductive via coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon, wherein an uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

12. The method of claim 11 , further comprising:
forming a dielectric plug disposed adjacent the conductive via and breaking continuity of one of the plurality of conductive lines, the dielectric plug having an uppermost surface planar with the uppermost surface of the via hardmask.

13. The method of claim 12 , wherein the dielectric plug is composed of a material different than the ILD layer.

14. The method of claim 12 , wherein the dielectric plug is composed of a same material as the ILD layer and is continuous with the ILD layer.

15. The method of claim 11 , wherein the conductive tab is continuous with the two of the plurality of conductive lines.

16. The method of claim 11 , wherein the plurality of conductive lines has a pitch of 20 nanometers or less.

17. The method of claim 11 , wherein each of the plurality of conductive lines has a width of 10 nanometers or less.

18. A method of fabricating a back end of line (BEOL) metallization layer for a semiconductor structure, the method comprising:
forming an inter-layer dielectric (ILD) layer disposed above a substrate;
forming a plurality of conductive lines disposed in the ILD layer along a first direction;
forming a conductive tab disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction; and
forming a dielectric plug breaking continuity of one of the plurality of conductive lines, wherein an uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the dielectric plug is planar with one another, and wherein the dielectric plug is composed of a material different than the ILD layer.

19. The method of claim 18 , wherein the conductive tab is continuous with the two of the plurality of conductive lines.

20. The method of claim 18 , wherein the plurality of conductive lines has a pitch of 20 nanometers or less.

21. The method of claim 18 , wherein each of the plurality of conductive lines has a width of 10 nanometers or less.

22. A method of fabricating a computing device, the method comprising:
providing a board; and
coupling a component to the board, the component including an integrated circuit structure, the integrated circuit comprising a back end of line (BEOL) metallization layer for a semiconductor structure, the BEOL metallization layer comprising:
an inter-layer dielectric (ILD) layer disposed above a substrate;
a plurality of conductive lines disposed in the ILD layer along a first direction; and
a conductive tab disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction; and
a conductive via coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon, wherein an uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

23. The method of claim 22 , further comprising:
coupling a memory coupled to the board.

24. The method of claim 22 , further comprising:
coupling a communication chip coupled to the board.

25. The method of claim 22 , further comprising:
coupling a camera coupled to the board.

Assignees

• Tahoe Res Ltd

Inventors

• Lin Kevin
• Bristol Robert L
• Schenker Richard E

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title