Self-aligned via and plug patterning for back end of line (BEOL) interconnects

Patent metadata

Field	Value
Publication number	US-9666451-B2
Application number	US-201314914095-A
Country	US
Kind code	B2
Filing date	Sep 27, 2013
Priority date	Sep 27, 2013
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure. Each dielectric line of the grating of the second structure has a continuous region of a third dielectric material distinct from the alternating distinct regions of the first dielectric material and the second dielectric material.

First claim

What is claimed is:

1. An interconnect structure for an integrated circuit, the interconnect structure comprising:
a first layer of the interconnect structure disposed above a substrate, the first layer comprising a grating of alternating metal lines and dielectric lines in a first direction; and
a second layer of the interconnect structure disposed above the first layer, the second layer comprising a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction, wherein each metal line of the grating of the second layer is disposed on a recessed dielectric line comprising alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure, and wherein each dielectric line of the grating of the second layer comprises a continuous region of a third dielectric material distinct from the alternating distinct regions of the first dielectric material and the second dielectric material.

2. The interconnect structure of claim 1 , wherein a metal line of the second layer is electrically coupled to a metal line of the first layer by a via having a center directly aligned with a center of the metal line of the first layer and with a center of the metal line of the second layer.

3. The interconnect structure of claim 1 , wherein a metal line of the second layer is disrupted by a plug having a center directly aligned with a center of a dielectric line of the first layer.

4. The interconnect structure of claim 1 , wherein none of the first dielectric material, the second dielectric material, and the third dielectric material are the same.

5. The interconnect structure of claim 1 , wherein only two of the first dielectric material, the second dielectric material, and the third dielectric material are the same.

6. The interconnect structure of claim 1 , wherein the alternating distinct regions of the first dielectric material and the second dielectric material are separated by seams, and wherein the continuous region of the third dielectric material is separated from the alternating distinct regions of the first dielectric material and the second dielectric material by seams.

7. The interconnect structure of claim 1 , wherein all of the first dielectric material, the second dielectric material, and the third dielectric material are the same.

8. A method of fabricating an interconnect structure for an integrated circuit, the method comprising:
providing a previous layer metallization structure comprising an alternating metal line and dielectric line first grating pattern having a first direction;
forming a dielectric line second grating pattern above the previous layer metallization structure, the dielectric line second grating pattern having a second direction, perpendicular to the first direction;
forming a sacrificial structure above the first grating pattern and between the dielectric lines of the second grating pattern;
replacing portions of the sacrificial structure above and aligned with the metal lines of the first grating pattern with a first dielectric layer, and replacing portions of the sacrificial structure above and aligned with the dielectric lines of the first grating pattern with a second dielectric layer;
forming one or more conductive vias in the first dielectric layer;
recessing portions of the first and second dielectric layers; and
forming a plurality of metal lines in the recessed portions of the first and second dielectric layers, coupled with the one or more conductive vias, the plurality of metal lines having the second direction.

9. The method of claim 8 , further comprising:
forming one or more plug locations in the second dielectric layer.

10. The method of claim 8 , wherein a metal line of the plurality of metal lines in the recessed portions of the first and second dielectric layers is electrically coupled to a metal line of the previous layer metallization structure by one of the one or more conductive vias, the conductive via having a center directly aligned with a center of the metal line of the previous layer metallization structure and with a center of the metal line of the plurality of metal lines in the recessed portions of the first and second dielectric layers.

11. The method of claim 8 , wherein forming the plurality of metal lines comprises forming and planarizing a metal layer.

12. The method of claim 8 , further comprising:
forming an air-gap structure amongst the plurality of metal lines in the recessed portions of the first and second dielectric layers by removing the dielectric lines of the second grating pattern.

13. The method of claim 8 , wherein forming the sacrificial structure above the first grating pattern and between the dielectric lines of the second grating pattern comprises using a directed self-assembly (DSA) technique.

14. The method of claim 13 , wherein using the DSA technique comprises forming a 50-50 diblock polystyrene-polymethyl methacrylate (PS-PMMA) copolymer.

15. The method of claim 8 , wherein forming the sacrificial structure above the first grating pattern and between the dielectric lines of the second grating pattern comprises using a selective growth technique.

16. The method of claim 8 , wherein forming the first dielectric layer and the second dielectric material layer comprises forming a different material for each layer.

17. The method of claim 8 , wherein forming the first dielectric layer and the second dielectric material layer comprises forming a same material for each layer.

18. A method of fabricating an interconnect structure for an integrated circuit, the method comprising:
providing a previous layer metallization structure comprising an alternating metal line and dielectric line first grating pattern having a first direction;
forming a dielectric line second grating pattern above the previous layer metallization structure, the dielectric line second grating pattern having a second direction, perpendicular to the first direction;
forming a polymer structure above the first grating pattern and within the second grating pattern, the polymer structure comprising a first polymer species disposed above and aligned with the metal lines of the first grating pattern and a second polymer species disposed above and aligned with the dielectric lines of the first grating pattern;
removing the first polymer species from the polymer structure;
forming a first permanent dielectric layer above and aligned with the metal lines of the first grating pattern, and adjacent to the second polymer species;
replacing one or more regions of the first permanent dielectric layer with a conductive via; and, subsequently,
removing the second polymer species from the polymer structure to provide openings above and aligned with the dielectric lines of the first grating pattern;
forming a second permanent dielectric layer above and aligned with the dielectric lines of the first grating pattern;
protecting one or more plug locations by forming a hardmask pattern on portions of the second permanent dielectric layer;
recessing exposed portions of the first and second permanent dielectric layers, selective to the hardmask pattern; and
forming a metal layer in the recessed portions of the first and second permanent dielectric layers.

19. The method of claim 18 , further comprising:
removing the dielectric lines of the second grating pattern to form an air-gap structure.

20

Assignees

• Intel Corp

Inventors

• Wallace Charles H
• Nyhus Paul A

Classifications

• H10W70/635

  Through-vias · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title