Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects

Patent metadata

Field	Value
Publication number	US-9548269-B2
Application number	US-201514931175-A
Country	US
Kind code	B2
Filing date	Nov 3, 2015
Priority date	Dec 20, 2013
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an example, a method of fabricating an interconnect structure for an integrated circuit involves forming a first hardmask layer above an interlayer dielectric layer disposed above a substrate. The first hardmask layer includes a plurality of first hardmask lines having a first grating in a first direction and comprising one or more sacrificial materials interleaved with the first grating. The method also involves forming a second hardmask layer above the first hardmask layer. The second hardmask layer includes a plurality of second hardmask lines having a second grating in a second direction, diagonal to the first direction. The method also involves, using the second hardmask layer as a mask, etching the first hardmask layer to form a patterned first hardmask layer. The etching involves removing a portion of the one or more sacrificial materials.

First claim

What is claimed is:

1. An interconnect structure for an integrated circuit, the interconnect structure comprising: an interlayer dielectric layer disposed above a substrate; and
a grating structure disposed above the interlayer dielectric layer and comprising co-planar alternating pluralities of dielectric hardmask lines and conductive lines, wherein one or more of the plurality of conductive lines extends into the interlayer dielectric layer, and one or more of the plurality of conductive lines does not extend into the interlayer dielectric layer, and wherein the plurality of conductive lines has a constant pitch between a first conductive line and a successive second conductive line and between the successive second conductive line and a successive third conductive line wherein one of the one or more of the plurality of conductive lines that extends into the interlayer dielectric layer extends only partially into the interlayer dielectric layer to provide a conductive metal line for a metallization layer comprising the interlayer dielectric layer.

2. The interconnect structure of claim 1 , wherein one of the one or more of the plurality of conductive lines that extends into the interlayer dielectric layer extends entirely through the interlayer dielectric layer to provide a conductive via to an underlying metallization layer disposed between the substrate and the interlayer dielectric layer.

3. The interconnect structure of claim 1 , wherein the grating structure is disposed on the interlayer dielectric layer.

4. An interconnect structure for an integrated circuit, the interconnect structure comprising: an interlayer dielectric layer disposed above a substrate; and
a grating structure disposed above the interlayer dielectric layer and comprising co-planar alternating pluralities of dielectric hardmask lines and conductive lines, wherein one or more of the plurality of conductive lines extends into the interlayer dielectric layer, and one or more of the plurality of conductive lines does not extend into the interlayer dielectric layer, and wherein the plurality of conductive lines has a constant width for a first conductive line, for a successive second conductive line, for a successive third conductive line, for a successive fourth conductive line, and for a successive fifth conductive line wherein one of the one or more of the plurality of conductive lines that extends into the interlayer dielectric layer extends only partially into the interlayer dielectric layer to provide a conductive metal line for a metallization layer comprising the interlayer dielectric layer.

5. The interconnect structure of claim 4 , wherein one of the one or more of the plurality of conductive lines that extends into the interlayer dielectric layer extends entirely through the interlayer dielectric layer to provide a conductive via to an underlying metallization layer disposed between the substrate and the interlayer dielectric layer.

6. The interconnect structure of claim 4 , wherein the grating structure is disposed on the interlayer dielectric layer.

7. An interconnect structure for an integrated circuit, the interconnect structure comprising: an interlayer dielectric layer disposed above a substrate; and
a grating structure disposed above the interlayer dielectric layer and comprising co-planar alternating pluralities of dielectric hardmask lines and conductive lines, wherein one or more of the plurality of conductive lines extends into the interlayer dielectric layer, and one or more of the plurality of conductive lines does not extend into the interlayer dielectric layer, wherein the plurality of conductive lines has a constant pitch between a first conductive line and a successive second conductive line and between the successive second conductive line and a successive third conductive line, and wherein the plurality of conductive lines has a constant width for the first conductive line, for the successive second conductive line, and for the successive third conductive line wherein one of the one or more of the plurality of conductive lines that extends into the interlayer dielectric layer extends only partially into the interlayer dielectric layer to provide a conductive metal line for a metallization layer comprising the interlayer dielectric layer.

8. The interconnect structure of claim 7 , wherein one of the one or more of the plurality of conductive lines that extends into the interlayer dielectric layer extends entirely through the interlayer dielectric layer to provide a conductive via to an underlying metallization layer disposed between the substrate and the interlayer dielectric layer.

9. The interconnect structure of claim 7 , wherein the grating structure is disposed on the interlayer dielectric layer.

Assignees

• Myers Alan M
• Singh Kanwal Jit
• Bristol Robert L
• Chawla Jasmeet S
• Intel Corp

Inventors

• Myers Alan M
• Singh Kanwal Jit
• Bristol Robert L
• Chawla Jasmeet S

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title