Gradient metal liner for interconnect structures
US-2024332075-A1 · Oct 3, 2024 · US
Method of manufacturing a semiconductor device
US8946077B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8946077-B2 |
| Application number | US-201414158223-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 17, 2014 |
| Priority date | Jan 22, 2013 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a semiconductor device, the method comprising: forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction; forming a first insulation layer filling the slender hole between the plurality of conductive lines; forming a plurality of first isolated holes separated from one another between the plurality of conduct…
Assignees
Inventors
Classifications
Electricity · mapped topic
- H10W20/098Primary
Electricity · mapped topic
- H10D64/011Primary
Electricity · mapped topic
- H01L21/76829Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8946077B2 cover?
- A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated fro…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W20/098. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).