System, apparatus and method for globally aware reactive local power control in a processor

Patent metadata

Field	Value
Publication number	US-11853144-B2
Application number	US-202217664083-A
Country	US
Kind code	B2
Filing date	May 19, 2022
Priority date	Nov 22, 2019
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of processing circuits to execute instructions; and
a global control circuit to assert a global violation signal to the plurality of processing circuits in response to a determination that a combined power consumption of the plurality of processing circuits has exceeded a global current budget,
wherein each processing circuit of the plurality of processing circuits includes a local control circuit to, in response to a determination that a power consumption of the each processing circuit has exceeded a local current budget allocated to the each processing circuit, enable the each processing circuit to exceed the local current budget allocated to the each processing circuit unless the global violation signal is asserted.

2. The processor of claim 1 , wherein the local control circuit is further to:
in response to the determination that the local current budget for the processing circuit has been exceeded, throttle the processing circuit while the global violation signal is asserted.

3. The processor of claim 1 , wherein the local control circuit is further to:
in response to the determination that the local current budget for the processing circuit has been exceeded, prevent the processing circuit from being throttled while the global violation signal is unasserted.

4. The processor of claim 1 , wherein the local control circuit is further to:
assert a local violation signal in response to the determination that the local current budget for the processing circuit has been exceeded, wherein the local violation signal is sent from the local control circuit to the global control circuit.

5. The processor of claim 4 , wherein the global control circuit is further to:
receive the local violation signal from the local control circuit in at least one processing circuit; and
generate the global violation signal after receiving the local violation signal from the local control circuit in the at least one processing circuit.

6. The processor of claim 1 , wherein the global control circuit is included in a power controller of the processor.

7. The processor of claim 6 , wherein the plurality of processing circuits are divided into at least a first partition and a second partition, wherein the power controller is to allocate a first current budget to the first partition and allocate a second current budget to the second partition.

8. A non-transitory machine-readable medium having stored thereon instructions executable to:
determine, by a local control circuit of a first processing circuit of a processor, whether a current consumption of the first processing circuit exceeds a local current budget allocated to the first processing circuit, wherein the processor comprises a plurality of processing circuits;
determine, by the local control circuit, whether a global violation signal is currently asserted to indicate that a combined power consumption of the plurality of processing circuits currently exceeds a global current budget; and
in response to a determination that the current consumption of the first processing circuit exceeds the local current budget and the global violation signal is not currently asserted, enable the processing circuit to exceed the local current budget.

9. The machine-readable medium of claim 8 , including instructions executable to:
in response to the determination that the local current budget for the first processing circuit has been exceeded, the local control circuit throttling the first processing circuit while the global violation signal is currently asserted.

10. The machine-readable medium of claim 8 , including instructions executable to:
in response to the determination that the local current budget for the first processing circuit has been exceeded, the local control circuit preventing throttling of the first processing circuit while the global violation signal is unasserted.

11. The machine-readable medium of claim 8 , wherein the global violation signal is asserted by a global control circuit included in the processor.

12. The machine-readable medium of claim 11 , including instructions executable to:
the local control circuit asserting a local violation signal in response to the determination that the local current budget for the first processing circuit has been exceeded, wherein the local violation signal is sent from the local control circuit to the global control circuit.

13. The machine-readable medium of claim 11 , wherein the global control circuit is included in a power controller of the processor.

14. The machine-readable medium of claim 13 , wherein the plurality of processing circuits are divided into at least a first partition and a second partition, wherein the power controller is to allocate a first current budget to the first partition and allocate a second current budget to the second partition.

15. A system comprising:
a system on chip (SoC) comprising:
a plurality of processing circuits to execute instructions; and
a global control circuit to assert a global violation signal to the plurality of processing circuits in response to a determination that a combined power consumption of the plurality of processing circuits has exceeded a global current budget,
wherein each processing circuit of the plurality of processing circuits includes a local control circuit to, in response to a determination that a power consumption of the each processing circuit has exceeded a local current budget allocated to the each processing circuit:
enable the each processing circuit to operate above the local current budget when the global violation signal is absent; and
throttle the each processing circuit when the global violation signal is asserted.

16. The system of claim 15 , wherein the local control circuit is further to:
in response to the determination that the local current budget for the processing circuit has been exceeded, prevent the processing circuit from being throttled while the global violation signal is unasserted.

17. The system of claim 15 , wherein the local control circuit is further to:
assert a local violation signal in response to the determination that the local current budget for the processing circuit has been exceeded, wherein the local violation signal is sent from the local control circuit to the global control circuit.

18. The system of claim 17 , wherein the global control circuit is further to:
receive the local violation signal from the local control circuit in at least one processing circuit; and
generate the global violation signal after receiving the local violation signal from the local control circuit in the at least one processing circuit.

19. The system of claim 15 , wherein the global control circuit is included in a power controller of the processor.

20. The system of claim 19 , wherein the plurality of processing circuits are divided into at least a first partition and a second partition, wherein the power controller is to allocate a first current budget to the first partition and allocate a second current budget to the second partition.

Assignees

• Intel Corp

Inventors

• Dai Jianwei
• Pawlowski David
• Purandare Adwait
• Varma Ankush

Classifications

• G06F1/3234 Primary

  Power saving characterised by the action undertaken · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/329 Primary

  by task scheduling · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title