Controlling temperature of multiple domains of a multi-domain processor using a cross-domain margin

Patent metadata

Field	Value
Publication number	US-9235254-B2
Application number	US-201313780087-A
Country	US
Kind code	B2
Filing date	Feb 28, 2013
Priority date	Sep 28, 2011
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a first domain including at least one core to execute instructions;
a second domain including at least one functional unit to execute a specialized function, wherein the first and second domains are located on a single die and can operate at independent frequencies; and
a power control unit (PCU) coupled to the first and second domains, the PCU including a thermal logic to cause a reduction in a frequency of the second domain by a frequency bin after a plurality of iterations in which a temperature of the first domain exceeds a sum of a throttle threshold and a cross-domain margin, wherein the cross-domain margin is a programmable temperature margin parameter stored in a non-volatile storage of the processor corresponding to a marginal level above the throttle threshold for the first domain at which a power consumption of the second domain is to be reduced to allow the temperature of the first domain to be reduced, the frequency bin corresponding to a smallest multiple by which the second domain frequency can change.

2. The processor of claim 1 , wherein the thermal logic is to update a value of a counter for the second domain when the first domain is determined to exceed the sum.

3. The processor of claim 2 , wherein the thermal logic is to cause the second domain frequency to be reduced by the frequency bin when the counter value is equal to N.

4. The processor of claim 3 , where N is controllable by a user.

5. The processor of claim 1 , wherein the thermal logic is to cause the reduction in the second domain frequency if the second domain temperature is greater than a throttle threshold for the second domain.

6. The processor of claim 1 , wherein the thermal logic is to cause a reduction in a frequency of the first domain if a temperature of the second domain exceeds a sum of a throttle threshold for the second domain and the cross-domain margin.

7. The processor of claim 1 , wherein the non-volatile storage is to store the throttle threshold and the cross-domain margin, wherein the throttle threshold is of a different value than a junction temperature of the processor.

8. A non-transitory storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
determining, for a plurality of iterations, in a controller of a multi-domain processor, that a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, wherein the cross-domain margin is a programmable temperature margin parameter stored in a non-volatile storage of the multi-domain processor corresponding to a marginal level above the throttle threshold for the second domain at which a power consumption of a first domain of the multi-domain processor is to be reduced to allow a temperature of the second domain to be reduced; and
responsive to the temperature of the second domain being greater than the sum for the plurality of iterations, reducing a frequency of the first domain by a frequency bin, otherwise maintaining a current frequency of the first domain, the frequency bin corresponding to a smallest multiple by which the first domain frequency can change.

9. The non-transitory storage medium of claim 8 , wherein the method further comprises reducing the first domain frequency if a temperature of the first domain is greater than the throttle threshold.

10. The non-transitory storage medium of claim 8 , wherein the method further comprises updating a value of a counter for the first domain when the second domain is determined to exceed the sum, and updating the counter value when the first domain is determined to exceed a throttle threshold for the first domain.

11. The non-transitory storage medium of claim 10 , wherein reducing the first domain frequency includes reducing the first domain frequency by the frequency bin of the first domain when the counter value equals N.

12. The non-transitory storage medium of claim 8 , wherein the method further comprises:
determining whether a temperature of the first domain is greater than the sum; and
if so, reducing a frequency of the second domain by a second selected amount, otherwise maintaining a current frequency of the second domain.

13. A system comprising:
a multi-domain processor including a first domain having a plurality of cores, a second domain including at least one graphics processing engine, and a system agent domain including a power controller, wherein the power controller is to reduce a frequency of the first domain by a selected amount when a temperature of the second domain is greater than a sum of a throttle threshold and a cross-domain margin, and otherwise to maintain a current frequency of the first domain, wherein the throttle threshold is dynamically controllable based on aging of the multi-domain processor and the cross-domain margin comprises a programmable temperature margin parameter stored in a non-volatile storage of the multi-domain processor corresponding to a marginal level above the throttle threshold for the second domain at which a power consumption of the first domain is to be reduced to allow the temperature of the second domain to be reduced, wherein the power controller is to update a value of a counter for the first domain when the second domain is determined to exceed the sum, and to reduce the first domain frequency by a bin frequency when the counter value equals N.

Assignees

• Intel Corp

Inventors

• Ananthakrishnan Avinash N
• Ziv Tomer
• Rajwan Doron
• Rotem Efraim

Classifications

• G06F1/206 Primary

  comprising thermal management · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• Y02B60/1275

  Cross-Sectional Technologies · mapped topic

• G06F1/3234 Primary

  Power saving characterised by the action undertaken · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title