Mapping A Performance Request To An Operating Frequency In A Processor

Patent metadata

Field	Value
Publication number	US-2016259392-A1
Application number	US-201615135682-A
Country	US
Kind code	A1
Filing date	Apr 22, 2016
Priority date	Jun 25, 2013
Publication date	Sep 8, 2016
Grant date	—

Abstract

In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.

First claim

1 . (canceled)

2 . An apparatus comprising:
a first processor including a first plurality of cores; a second processor including a second plurality of cores; and a power controller to control power consumption of the first processor and the second processor, the power controller including:
a first logic
to receive performance level information,
to use a table to map the performance level information to a target operating frequency for at least the first processor based at least in part on the performance level information, and
to adjust the target operating frequency based at least in part on at least one first processor constraint; and

a frequency control logic to cause the first processor to operate at the adjusted target operating frequency.

3 . The apparatus of claim 2 , wherein the first logic to adjust the target operating frequency based at least in part on at least one second processor constraint, and the frequency control logic to cause the second processor to operate at the adjusted target operating frequency.

4 . The apparatus of claim 3 , wherein the at least one second processor constraint comprises a thermal constraint.

5 . The apparatus of claim 2 , wherein the power controller comprises a first power controller to control power consumption of the first processor and a second power controller to control power consumption of the second processor.

6 . The apparatus of claim 2 , wherein the first processor comprises a microprocessor.

7 . The apparatus of claim 6 , wherein the second processor comprises a graphics processing engine.

8 . The apparatus of claim 1 , wherein the performance level information comprises balancing information from a user.

9 . The apparatus of claim 2 , further comprising at least one interface.

10 . The apparatus of claim 2 , wherein the power controller is to cause at least a portion of the first processor to operate at one or more of a P0 performance state and a P1 performance state.

11 . An apparatus comprising:
first processor means including a first plurality of cores; second processor means including a second plurality of cores; and power control means for controlling power consumption of the first processor means and the second processor means, the power control means including:
means for receiving performance level information,
means for mapping the performance level information to a target operating frequency for at least the first processor means based at least in part on the performance level information,
means for adjusting the target operating frequency based at least in part on at least one first constraint, and
means for causing the first processor means to operate at the adjusted target operating frequency.

12 . The apparatus of claim 11 , further comprising means for causing the second processor means to operate at the adjusted target operating frequency.

13 . The apparatus of claim 11 , wherein the power control means comprises first power control means for controlling power consumption of the first processor means and second power control means for controlling power consumption of the second processor means.

14 . The apparatus of claim 11 , wherein the first processor means comprises a microprocessor and the second processor means comprises a graphics processing engine.

15 . The apparatus of claim 11 , wherein the performance level information comprises balancing information from a user.

16 . The apparatus of claim 11 , wherein the power control means for causing at least a portion of the first processor means to operate at one or more of a P0 performance state and a P1 performance state.

17 . A system comprising:
a processor having a first plurality of cores, a second plurality of cores, and a controller to control power consumption of the first plurality of cores and the second plurality of cores, the controller including a first logic to receive performance level information, to use a table to map the performance level information to a target operating frequency for at least a first one of the first plurality of cores based at least in part on the performance level information, and to adjust the target operating frequency based at least in part on a first constraint, the controller further including a frequency control logic to cause the at least first one of the plurality of first cores to operate at the adjusted target operating frequency; a dynamic random access memory (DRAM) coupled to the processor; an audio device; and a wireless transceiver.

18 . The system of claim 17 , wherein the system comprises a touch-enabled device.

19 . The system of claim 18 , wherein the touch-enabled device comprises a smartphone.

20 . The system of claim 17 , further comprising a second controller to interface with one or more peripheral devices.

21 . The system of claim 20 , wherein the one or more peripheral devices comprises at least one input/output device.

Assignees

• Intel Corp

Inventors

• Weissmann Eliezer
• Rotem Efraim
• Diefenbaugh Paul
• Therien Guy
• Rosenzweig Nir

Classifications

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title